Analysis and Characterization of Capacitance Variation Using Capacitance Measurement Array

Abstract

To address the need for direct extraction of the capacitance of a chip, a capacitance measurement array (CMA) has been developed. The operation of the CMA is based on the charge-based capacitance measurement (CBCM) technique. The CMA chip consists of 144 CBCM array units (CAU) and each CAU is designed to measure eight individual capacitors. Element selection and precise measurement are achieved using three-stage transmission gates with four address lines, to ensure a measurement accuracy for capacitor of 1 fF. Different components of the capacitance measurement are addressed and the parameters of CAU are varied to determine the individual influence of these factors. Different physical capacitor shapes are examined to show the capacitance variation as a result of changes to the horizontal and vertical dimensions. MOS transistors with different channel widths are used to illustrate the driving capability influence. The chip is fabricated by a 180 nm CMOS process with six metallic interconnect layers. Based on the results of capacitance array measurement, the capacitance variation in the chip can also be determined. The full address capacitance is measured and the sample data are decomposed into systematic and random variation components using a third-order polynomial fitting for the chip.