Monitoring Test Structure for Plasma Process-Induced Charging Damage Using Charge-Based Capacitance Measurements

Abstract

A novel monitoring test structure is proposed for plasma process-induced charging damage (PID) based on charge-based capacitance measurement (CBCM), referred to as PID–CBCM. By eliminating antenna capacitance interferences, a remarkably smaller gate capacitance (tens of fF) can be obtained for effectively evaluating the influence of PID on metal oxide semiconductor field-effect transistors (MOSFETs). Moreover, the interface trap density can be extracted simultaneously using PID–CBCM implemented with modified charge pumping measurements. Furthermore, another type of PID–CBCM structure under unique measurement conditions has been developed to evaluate drain current (Id) as a function of gate voltage (Vg). The new structure works by extracting the threshold voltage (Vth) shifts on the basis of capacitance–voltage (C–V) characteristics after applying a stress voltage to the gate oxide of devices under test in the PID–CBCM structure. Based on these approaches, three meaningful characteristics of the PID are obtained: 1) Vth shifts extracted from C–V characteristics; 2) Vth shifts extracted from Id–Vg characteristics; and 3) interface trap density extracted from charge-pumping current. Thus, the effects of PID on MOSFET can be monitored over suitably small areas such as scribe-line and chip areas.