Charge-based Capacitance Measurement Research Articles

A Nondestructive Method of Extracting the Width and Thickness of Interconnects for a 40-nm Technology

In this paper, a simple and nondestructive method of modeling 40-nm interconnects is proposed. Traditional methods based on charge-based capacitance measurement model the interconnects by fitting the capacitance or resistance curves, first by assuming one constant process parameter, such as metal thickness, and then by extracting the metal width, metal spacing, and interlevel dielectric (ILD) thickness from certain test patterns that may therefore result in model inaccuracy while the transmission and scanning electron microscopy methods are both destructive and time consuming. The proposed new methodology directly extracts the metal width based on the metal resistance test structures, and then the metal thickness, metal spacing, and ILD thickness without any presumption. It is also nondestructive and fast, with a model accuracy higher than 95%. Furthermore, with the ensured accuracy of layout parameter extraction, the necessity of an accurate interconnect model in the 40 nm technology and beyond is emphasized.

Characterization and Modeling of Subfemtofarad Nanowire Capacitance Using the CBCM Technique

The experimental characterization of gate capacitance in nanoscale devices is challenging. We report an application of the charge-based capacitance measurement (CBCM) technique to measure the gate capacitance of a single-channel nanowire transistor. The measurement results are validated by 3-D electrostatic computations for parasitic estimation and 2-D self-consistent sp3s* d5 tight-binding computations for intrinsic gate capacitance calculations. The device simulation domains were constructed based on SEM and TEM images of the experimental device. The carefully designed CBCM technique thus emerges as a useful technique for measuring the capacitance and characterizing the transport in nanoscale devices.

Charge-Based Capacitance Measurement Technique for Nanoscale Devices: Accuracy Assessment Based on TCAD Simulations

In this brief, we carried out extensive mixed device and circuit-mode simulations to calibrate the charge-based capacitance measurement technique specifically for subfemtofarad nanowire-based device capacitance. The factors that influence the accuracy of the technique were identified.

Combining a Novel Charge-Based Capacitance Measurement (CBCM) Technique and Split $C$–$V$ Method to Specifically Characterize the STI Stress Effect Along the Width Direction of MOSFET Devices

The shallow trench isolation (STI) stress effect along the length direction on short-channel MOSFET devices has already been widely studied. However, the effect along the width direction has seldom been specifically analyzed. In this paper, we combine a novel charge-based capacitance measurement technique, which is used to extract the intrinsic of MOSFET devices, and the split capacitance-voltage method to extract the mobility of devices with various channel widths. Although it is already known that under the influence of compressive STI stress along the width direction the mobility of both NMOS and PMOS devices will degrade with decreasing width, it is the first time to quantify the impact of this STI stress component on MOSFET devices.

Charge-Based Capacitive Sensor Array for CMOS-Based Laboratory-on-Chip Applications

In this paper, we present a capacitive sensor array for highly integrated lab-on-chip (LoC) applications using the charge-based capacitance measurement method (CBCM). The core-CBCM sensor chip is designed and implemented in 0.18 micron CMOS process featuring an array of capacitive sensors; an offset cancellation module and a low complexity analog-to-digital converter (ADC). This sensor chip is incorporated with a microfluidic channel using direct-write fabrication process. We demonstrate the testing results using chemical solvents with known dielectric constants in order to show the viability of the proposed sensor chip for LoCs.

A Core-CBCM sigma delta capacitive sensor array dedicated to lab-on-chip applications

A sigma delta (ΣΔ) capacitive sensor is presented in this paper for highly integrated lab-on-chip (LoC) applications using charge based capacitance measurement method (CBCM). We put forward the design and implementation of sensor chip in 0.18 μm CMOS process featuring an array of capacitive sensors, an offset cancellation (OC) circuitry and a DC input first-order ΣΔ analog to digital converter (ADC). This sensor chip is incorporated with a microfluidic channel using direct-write fabrication process. The design, construction and experimental results are demonstrated using chemical solvents with known dielectric constants and polyelectrolyte solutions in order to show the viability of the proposed capacitive sensor for LoCs.

A 0.18-μm CMOS capacitive sensor Lab-on-Chip

In this paper, we put forward a capacitive sensor for Lab-on-Chip applications using a charge-based capacitance measurement (CBCM) method. This simple and highly sensitive capacitive sensor is implemented in the TSMC 0.18 CMOS process to which we incorporate microfluidic structures for chemical sensing. The post-layout simulation, fabrication and preliminary Lab-on-Chip testing results are also reported.

Charge-based capacitance measurement for bias-dependent capacitance

In this letter, charge-based capacitance measurement (CBCM) is applied to characterize bias-dependent capacitances in a CMOS transistor. Due to its special advantage of being free from the errors induced by charge injection, the operation of charge-injection-induced-error-free CBCM allows for the extraction of full-range gate capacitance from the accumulation region to the inversion region and the overlap capacitance of MOSFET devices with submicrometer dimensions.

Crosstalk-Based Capacitance Measurements: Theory and Applications

Geometry scaling increases the relative effect of coupling capacitances on performance, power, and noise so that they need to be carefully taken into account during process development, characterization, and monitoring. In the last decade, charge-based capacitance measurements (CBCMs) have been widely used to estimate on-chip wiring and coupling capacitances because of their accuracy and simplicity. We provide a thorough theoretical and experimental study of CBCMs applied to the selective extraction of cross-coupling capacitances. We take a historical perspective starting from the original CBCM approach proposed by Chen in 1996, and we present a new technique for crosstalk-based capacitance measurements (CTCMs). CTCMs improve the accuracy and usability of CBCMs while reducing the complexity of the test structures. We present the theory of CTCM, we provide experimental results demonstrating its improved accuracy, and we discuss its application to a wide range of process monitoring and testing tasks. Experimental results are used throughout the paper to support the discussion.

Interconnect Capacitance Characterization Using Charge-Injection-Induced Error-Free (CIEF) Charge-Based Capacitance Measurement (CBCM)

In this work, we describe a novel operation of charge-injection-induced error-free charge-based capacitance measurement (CIEF CBCM) method. This method has the simplest test structure among various CBCM methods by using only one N/PMOS pair. CIEF CBCM has the advantage of being free from charge-injection-induced errors and of efficient layout area usage. It is very suitable for industrial applications for large amounts of accurate capacitance characterizations with a limited layout area. Besides, CIEF CBCM is also implemented for investigating the impact of floating dummy metal fills on interconnect capacitance directly from silicon data.

Feature-Scale Process Simulation and Accurate Capacitance Extraction for the Backend of a 100-nm Aluminum/TEOS Process

One of the challenges that technology computer-aided design must meet currently is the analysis of the performance of groups of components, interconnects, and, generally speaking, large parts of the IC. This enables predictions that the simulation of single components cannot achieve. In this paper, we focus on the simulation of backend processes, interconnect capacitances, and time delays. The simulation flows start from the blank wafer surface and result in device information for the circuit designer usable from within SPICE. In order to join topography and backend simulations, deposition, etching, and chemical mechanical planarization processes in the various metal lines are used to build up the backend stack, starting from the flat wafer surface. Depending on metal combination, line-to-line space, and line width, thousands of simulations are required whose results are stored in a database. Finally, we present simulation results for the backend of a 100-nm process, where the influence of void formation between metal lines profoundly impacts the performance of the whole interconnect stack, consisting of aluminum metal lines, and titanium nitride local interconnects. Scanning electron microscope images of test structures are compared to topography simulations, and very good agreement is found. Moreover, charge-based capacitance measurements were carried out to validate the capacitance extraction, and it was found that the error is smaller than four percent. These simulations assist the consistent fabrication of voids, which is economically advantageous compared to low-/spl kappa/ materials, which suffer from integration problems.

A Novel Simple CBCM Method Free From Charge Injection-Induced Errors

In this letter, we propose a charge injection-induced error-free charge-based capacitance measurement method (CIEF CBCM). This novel method uses only one n/pMOS pair to characterize the small interconnect capacitance. It has the simplest test structure among various CBCM methods. More importantly, the CIEF CBCM method is free from the errors induced by charge injection. Besides, only one additional pad is needed for one additional capacitor under the test by this method, and it is the most efficient method for process characterization and monitoring.

Charge-based capacitance measurements (CBCM) on MOS devices

A new simple method of measuring capacitance-voltage characteristics of MOS devices is presented. Proceeding from the charge-based capacitance measurement technique suggested recently, a compact test structure with high resolution has been developed, which only requires measurement of do quantities. The method was tested on a 0.6-/spl mu/m CMOS process with small and large area capacitors and compared to well-known high-frequency capacitance-voltage results. Beside using a reference structure, a second means of extracting parasitic effects is demonstrated for small structures. The test structure allows measurements in a wide frequency range with high accuracy and low noise contribution at small capacitance levels.

Analytical modeling and characterization of deep-submicrometer interconnect

This work addresses two fundamental concepts regarding deep-submicrometer interconnect. First, characterization of on-chip interconnect is considered with particular attention to ultrasmall capacitance measurement and in-situ noise evaluation techniques. An approach to measuring femto-Farad level wiring capacitances is presented that is based on the concept of supplying and removing charge with active devices. The method, called the charge-based capacitance measurement (CBCM) technique, has the advantages of being compact, having high-resolution, and being very simple. We also present a novel time-domain measurement scheme for on-chip crosstalk noise that is based on the use of cascaded high-speed differential pairs to compare a user-defined reference voltage to the unknown noise peak value. The noise measurement technique complements a delay measurement to directly evaluate the impact of capacitive coupling on delay for various victim and aggressor driver sizes as well as arbitrary waveform timing and phase alignments. The second area of emphasis in this work is analytical interconnect modeling. Several important effects are modeled, including a rigorous crosstalk noise model that also includes a timing-level model. Results from this noise model show it to provide accuracy within 10% of SPICE for a wide range of input parameters. The noise model can also be calibrated and verified with comparison to the noise measurement scheme described in this work. A fast Monte Carlo approach to modeling the circuit impact of back-end process variation is presented providing a better depiction of real 3-/spl sigma/ performance spreads compared to the traditional skew-corner approach. Finally. A comprehensive system-level performance model called Berkeley Advanced Chip Performance Calculator (BACPAC) is developed that accounts for a number of relevant deep-submicrometer system design issues. BACPAC has been implemented online and is useful in exploring the capabilities of future very large scale integration systems as well as determining trends and tradeoffs inherent in the design process.

Application of Charge-Based Capacitance Measurement Technique in Characterization of Hydrogen Silsesquioxane

The charge-based capacitance measurement technique was employed to measure femtofarad-level interconnect capacitance, to evaluate the dielectric constant of hydrogen silsesquioxane (HSQ) intermetal dielectric, and to study dielectric anisotropy of HSQ. It is demonstrated that high temperature processes during back end integration will affect the dielectric property of HSQ and therefore an alternative thermal curing condition is required. An over 25% reduction in intracapacitance for 0.32 μm spaced metal lines has been achieved. The underlying dielectric liner has insignificant impact on parasitic interconnect capacitance. HSQ exhibits anisotropic dielectric behavior which is desirable in minimizing both resistance capacitance delay and cross talk. © 2001 The Electrochemical Society. All rights reserved.

Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and three-dimensional simulation

This paper examines the recently introduced charge-based capacitance measurement (CBCM) technique through use of a three-dimensional (3-D) interconnect simulator. This method can be used in conjunction with simulation at early process development stages to provide designers with accurate parasitic interconnect capacitances. Metal to substrate, interwire, and interlayer capacitances are each discussed and overall close agreement is found between CBCM and 3-D simulation. Full process interconnect characterization is one possible application of this new compact, high-resolution test structure.