Characteristics Of MOS Transistors Research Articles

Revealing the Impact of Gate Area Scaling on Charge Trapping Employing SiO2Transistors

The operating characteristics of MOS transistors, such as the switching speed and power consumption, have been improved due to the increased reduction of the lateral dimensions. A further advantage of modern scaled nodes is that defects within the oxide and at the semiconductor/oxide interface are observed in a reduced number, however, they show an enhanced impact on the device characteristics. This leads to a substantially increased variability of the threshold voltages, sub-threshold swing, and carrier mobility when comparing nominally identical devices. As a consequence of this pronounced device-to-device variability, statistical analyses are required for studying the reliability of these technologies. By performing measurements on large sets of devices, statistical distributions of defect properties can be created to study the dependence of statistical quantities, like the link between the average threshold shift of a single emission event and the lateral device dimensions. In this work, the distributions of the contributions of defects on the device behavior are investigated, by making use of commercial pMOS and nMOS devices. The combined use of single-defect extractions and the defect-centric model (DCM) enables us to accurately extract valuable information for a whole technology. While existing approaches focus on either large-area or nanoscale nodes, our results hold for both regimes and are of high relevance for accurately describing the impact of charge traps which is mandatory for further improvement of the layout and performance of circuits.

Phase Noise Reduction in LC VCO’s Using an Array of Cross-Coupled Nanoscale MOSFETs and Intelligent Post-Fabrication Selection

Low-frequency mymargin noise, thermal noise, and dc characteristics of nanoscale MOS transistors with dimensions close to the process minimum are highly variable. This article demonstrates a phase noise (PN) reduction technique for LC voltage-controlled oscillators (VCOs) that use an intelligent post-fabrication selection of a subset of an array of near minimum-size cross-coupled transistor pairs with reduced low-frequency noise and thermal noise. Using the technique, the PN of a VCO is lowered from the maximum by 3.5 dB at 600-kHz, 1-MHz, and 3-MHz offsets from a 3.8-GHz carrier. The lowest PN of −122, −129, and −139.5 dBc/Hz at 600-kHz, 1-MHz, and 3-MHz offsets, respectively, from a 3.8-GHz carrier has been measured using the PLL method of the Keysight E5052B Signal Source Analyzer. The VCO prototype was fabricated in a 65-nm CMOS process and dissipates 7 mW of dc power. The maximum figure of merit (FoM), including PN, carrier frequency, and power consumption, is 193 dBc/Hz, and the FoM, including the VCO core area, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm {FoM}}_{A}$ </tex-math></inline-formula> , is 209 dBc/Hz.

Efficient Modeling of Charge Trapping at Cryogenic Temperatures—Part I: Theory

Charge trapping is arguably the most important detrimental mechanism distorting the ideal characteristics of MOS transistors, and nonradiative multiphonon (NMP) models have been demonstrated to provide a very accurate description. For the calculation of the NMP rates at room temperature or above, simple semiclassical approximations have been successfully used to describe this intricate mechanism. However, for the computation of charge transition rates at cryogenic temperatures, it is necessary to use the full quantum mechanical description based on Fermi’s golden rule. Since this is computationally expensive and often not feasible, we discuss an efficient method based on the Wentzel–Kramers–Brillouin (WKB) approximation in combination with the saddle point method and benchmark this approximation against the full model. We show that the approximation delivers excellent results and can, hence, be used to model charge trapping behavior at cryogenic temperatures.

Trap Recovery by in-Situ Annealing in Fully-Depleted MOSFET With Active Silicide Resistor

This work reports first original results on the impact of active in-situ electro-thermal recovery, on the electrical and low-frequency noise characteristics of N-type MOS transistor with thick high-k metal gate oxide, from 28 nm Fully Depleted Silicon-On-Insulator (FDSOI) process. In order to recover “typical” device characteristics, four cycles of local thermal annealing up to 590K are applied for 14 ms each, using an active silicide source. Experimental results reveal an important improvement of the “corner” transistor’s I-V behavior allowing the recovery of “typical” device characteristics. An increase of the maximum transconductance by 43% is obtained. In the same time, a typical device stays unaffected by this local annealing. Low-frequency noisemeasurements showa clear reduction of the 1/f noise and Random Telegraph Noise by almost one decade, after the electro-thermal recovery. This can explain the improvement of the electrical characteristics by annealing of defects.

Effect of Process-Related Impurities on the Electrophysical Parameters of a MOS Transistor

It is established that the electrophysical characteristics of MOS transistors largely depend on the quality of a gate dielectric. The presence of an extra built-in charge in the dielectric and fast surface states at the SiO2/Si interface leads to both an increased threshold voltage and decreased saturation current and voltage, decreased slopes of the characteristics of the MOS transistor in the linear and saturation regions, and a decreased structure conductance in the linear region. The gate leakage currents also increase. It is shown that the view and shape of the capacity–voltage characteristics are determined by the value of an extra positive charge in the bulk of the dielectric and the density of fast surface states at the Si/SiO2 interface. These values are correlated to the profile of the distribution of the surface concentration of the process-related impurities adsorbed at the wafer surface during the manufacturing of the device, which allows us to judge the quality of the materials used, adherence to the production conditions, and, if necessary, correct them opportunely as required.

Normalized Nonlinear Semiempirical MOST Model Used in Monolithic RF Class A-to-C PAs

This paper presents a simple but accurate normalized nonlinear large-signal semiempirical MOS transistor model to be used in monolithic RF Class A-to-C PAs. MOS transistor characteristics, saved in lookup tables, are extracted for different PVT corners, allowing the study of the PA performance spread. Model accuracy is ratified by the excellent matching obtained when comparing data algebraically calculated with electrical simulations of hundreds of PAs, and with the measurement data of a fabricated 2.4 GHz PA.

A differential class‐E power amplifier with dynamic body bias technique

AbstractA fully differential class‐E power amplifier (PA) for wireless body area network applications is presented in this article. A novel dynamic self‐adapting body bias (DSBB) technique is introduced to improve the switch‐on transition and on‐resistance characteristics of MOS transistors. The proposed circuit is fabricated in the TSMC 0.18‐μm RF CMOS process. Measurement results show that the DSBB PA achieves a power‐added efficiency (PAE) of 46.9% with an output power of 13.1 dBm at 900 MHz. Compared to the conventional body‐ground connection PA, PAE and output power are improved more than 6.6% and 4.2 mW, respectively.

Reliability Investigation of 0.18-μm SOI MOS Transistors at High Temperatures

In this paper, we estimate the basic parameters of 0.18-μm SOI MOS transistors in the temperature range from –60 to 300°С and investigate their reliability at high temperatures. The specific characteristics of SOI MOS transistors that manifest themselves at high temperatures should be taken into account when designing high-temperature integrated circuits in order to avoid their premature failures and improve the reliability of electronic devices.

Fixed Charge Control of Silylated Surface for Stiction-Free Drying with Surface Energy Reduction Process

Recently, a surface energy reduction process (SERP) for stiction-free drying is used for a high aspect pattern structure like shallow trench isolation (STI). The key technology of SERP is trimethylsilyl (TMS) groups termination of the device surface. To explain the electrical influence of TMS groups was found acceptable by measuring the planar capacitor flat-band voltage shift, and the threshold voltage characteristics of 1x-nm node MOS transistors.

Geometry and temperature effects on the threshold voltage characteristics of silicon nanowire MOS transistors

This work reports the observations of different geometry and temperature dependencies of electrical characteristics of silicon nanowire transistors with gate length of a couple microns. Several abnormal characteristics degradations were observed. As the gate lengths as well as the source/drain doping level of the devices under investigation were well beyond the punchthrough conditions, these observed characteristic degradations should not be due to conventional short-channel effects. We ascribed these observations to the charge transport along the corners/boundaries of the nanowires. Current enhancements were observed because of the higher mobility and larger density of states at the corners where the surface states have opposite effects on these parameters. Temperature dependence of the threshold voltage shows a linear decrease as the temperature increases. This trend is ascribed to the charge states at oxide/nanowire interfaces. Corners and surfaces of nanowire thus should play an important role for ultra-short nanowire transistors and that calls for shape of nanowire optimization for device design.

3-D-Stacked 16-Mpixel Global Shutter CMOS Image Sensor Using Reliable In-Pixel Four Million Microbump Interconnections With 7.6-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu \text{m}$ &lt;/tex-math&gt;&lt;/inline-formula&gt; Pitch

We have developed a 3-D-stacked 16-Mpixel, 3.8- $\mu \text{m}$ pitch, and global shutter (GS) CMOS image sensor with a 2-Mpixel 10 000-frames/s high-speed image-capturing mode, with four million reliable microbump interconnections. This sensor consists of a photodiode (PD) substrate and an in-pixel storage node substrate. The four PDs in the unit pixel circuit on the top substrate share one microbump interconnection in 7.6- $\mu \text{m}$ pitch. Each signal of the PDs is transferred to the corresponding storage node on the bottom substrate via the interconnection to achieve a GS function. The ratio of the parasitic light sensitivity of an in-pixel storage node and the light sensitivity of a PD is −180 dB, which is the best record for a CMOS image sensor with 3.8- $\mu \text{m}$ pixels. The image sensor was fabricated with a wafer-on-wafer bonding process technology. We confirmed that the bonding process did not harm the pixel or the MOS transistor characteristics and required no extra area, which means no restrictions on the layout design of microbumps or circuits. No reliability problems were observed in either a heat cycle test or a high temperature and high humidity test.

MTL‐based implementation of current‐mode CMOS RMS‐to‐DC converters

SummaryIn this paper, systematic implementation of current‐mode RMS‐to‐DC converters based upon MOS translinear (MTL) principle, utilizing symmetric cascoded MTL cell (SCMC) is proposed. Theory of operation and mathematical analysis of both explicit (direct) and implicit (indirect) techniques for realization of SCMC‐based RMS‐to‐DC converters are discussed. The SCMC includes a folded MTL loop and realizes an MTL equation. MTL principle utilizes the square law characteristics of saturated MOS transistors to realize square‐root domain (SRD) functions. The SCMC is constructed by two connected cascoded current mirrors and has a compact, symmetric, and multi‐purpose structure, with capability of implementing the circuits into the programmable and configurable structures. The proposed RMS‐to‐DC converters utilize the SCMC along with a configurable current mirror array. The required squaring and square‐rooting functions are realized using the SCMC, after proper configuration of the current mirror array. The proposed circuits have been implemented using a reconfigurable architecture fabricated in a 0.5 µm CMOS technology. Copyright © 2014 John Wiley &amp; Sons, Ltd.

FGMOS transistor based low voltage and low power fully programmable Gaussian function generator

In this paper floating gate MOS (FGMOS) transistor based fully programmable Gaussian function generator (GFG) is presented. The circuit combines the exponential characteristics of MOS transistor in...

(Invited) Study on Charge Storage and Optical Response of Hybrid Nanodots Floating Gate MOS Devices for Their Optoelectronic Application

We have designed and fabricated hybrid nanodots structures, in which Si quantum dots (QDs) and either Ni-silicide or Pt-silicide nanodots (NDs) are stacked with ultrathin SiO2 interlayer, as a novel functional floating gate (FG) to satisfy both multiple valued capability and large capacity on charge storage. Multiple-step charge injection to sililcide NDs through discrete energy states in Si-QDs and stable storage of many charges in deep potential wells in silicide NDs have been confirmed from electrical characteristics of MOS capacitors and transistors measured at room temperature. A unique optical response of the hybrid NDs FG to near-infrared light irradiation, which is caused by the transfer of photo-excited electrons from silicide NDs to Si-QDs, has also been demonstrated.

Fully Programmable Gaussian Function Generator Using Floating Gate MOS Transistor

Floating gate MOS (FGMOS) based fully programmable Gaussian function generator is presented. The circuit combines the tunable property of FGMOS transistor, exponential characteristics of MOS transistor in weak inversion, and its square law characteristic in strong inversion region to implement the function. Two-quadrant current mode squarer is the core subcircuit of Gaussian function generator that helps to implement full Gaussian function for positive as well as negative input current. FGMOS implementation of the circuit reduces the current mismatching error and increases the tunability of the circuit. The performance of circuit is verified at 1.8 V in TSMC 0.18 μm CMOS, BSIM3, and Level 49 technology by using Cadence Spectre simulator.

Improving the electrical characteristics of MOS transistors with CeO2/La2O3 stacked gate dielectric

In this work, the electrical characteristics of MOSFETs with CeO2/La2O3 gate dielectric stacks, where it was shown to have much lower amount of oxygen vacancy, were studied. We found that the negative threshold voltage shift in the La2O3-only transistors can be significantly suppressed. This improvement is attributed to the reduction of oxide charge density and to the dipole at the Si/La2O3 interface. Significant enhancement in channel mobility was also found for both NMOS and PMOS transistors. This latter improvement should be due to the silicon oxidation taking place at the La2O3/Si interface with the available of extra oxygen atoms from the CeO2 layer. We further found that the subthreshold slopes for NMOS and PMOS transistors with 2.5μm gate length were reduced to about 72mV/dec, which are significantly smaller than those of transistors without using CeO2 capping layer. This observation further confirms that the CeO2 capping layer also affects the La2O3/Si interface properties.

Influence of multi-finger layout on the subthreshold behavior of nanometer MOS transistors

This work studies the effects of number of gate finger on the DC subthreshold characteristics of multi-finger nanoscale MOS transistors. We found in not optimally-tempered nanoscale (gate length=90nm) MOS transistors that the significantly deteriorated subthreshold characteristics can be effectively improved by increasing the number of gate finger. This observation was explained with a modified subthreshold slope model based on voltage-doping transformation theory. Hence, the multi-finger structure does not only enhance the operation frequency, it also improves the subthreshold DC characteristics of the nanoscale MOS transistors.

Subthreshold Characteristics of MOS Transistors With $ \hbox{CeO}_{2}/\hbox{La}_{2}\hbox{O}_{3}$ Stacked Gate Dielectric

This letter reports the subthreshold characteristics of MOS transistors with the novel CeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /La <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> stacked gate dielectric. We found that the top CeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> capping layer does not only improve the bulk properties of La <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> by reducing the oxygen vacancies as a result of the reduction reaction of CeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> but also reduces the La <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /Si interface trap pronouncedly. We further identify the energy level of the interface traps by conducting temperature-dependent subthreshold slope measurements.

Electron trapping in 4H-SiC MOS capacitors fabricated by pre-oxidation nitrogen implantation

Incorporation of nitrogen (N) atoms by ion implantation prior to oxidation of SiO2/4H-SiC interfaces has been investigated by capacitance-voltage (C-V) characteristics and constant capacitance deep-level-transient spectroscopy (CCDLTS) measurements. The shift of the C-V curves to negative voltages can be explained by the partial activation of implanted N atoms during oxidation. The maximum amplitude of the CCDLTS spectra, proportional to the density of near-interface oxide traps, decreases with increasing N dose, but remains significantly larger than that of SiO2/SiC interfaces fabricated by post oxidation annealing in nitric oxide (NO). Intrinsic defects in the SiC epi-layer associated with implantation damage are also observed in N-implanted samples. In contrast, electron traps energetically close to the SiC conduction band, detected in NO annealed samples and presumably introduced during oxidation, are not observed in N-implanted samples. The improved transport characteristics of MOS transistors fabricated on N-implanted epi-layers compared to those fabricated by NO annealing is suggested to result from the effects of the greater N donor concentration and also possibly to the suppression of shallow electron traps in the SiC epilayer.

Effect of thin Si insertion at metal gate/high- k interface on electrical characteristics of MOS device with La 2O 3

The effect of a thin Si layer insertion at W/La 2O 3 interface on the electrical characteristics of MOS capacitors and transistors is investigated. A suppression in the EOT increase can be obtained with Si insertion, indicating the inhibition of diffusion of oxygen atoms into La 2O 3 layer by forming an amorphous La-silicate layer at the W/La 2O 3 interface. In addition, positive shifts in V fb and V th caused by Si insertion implies the formation of amorphous La-silicate layer at the top of La 2O 3 dielectrics reduces the positive fixed charges induced by the metal electrode. Consequently, a large improvement in mobility has been confirmed for both at peak value and at high E eff of 1 MV/cm with Si inserted nFETs. Although a degradation trend on EOT scaling has been observed, the insertion of thin Si layer is effective in pushing the scaling limit.