Geometry and temperature effects on the threshold voltage characteristics of silicon nanowire MOS transistors

Abstract

This work reports the observations of different geometry and temperature dependencies of electrical characteristics of silicon nanowire transistors with gate length of a couple microns. Several abnormal characteristics degradations were observed. As the gate lengths as well as the source/drain doping level of the devices under investigation were well beyond the punchthrough conditions, these observed characteristic degradations should not be due to conventional short-channel effects. We ascribed these observations to the charge transport along the corners/boundaries of the nanowires. Current enhancements were observed because of the higher mobility and larger density of states at the corners where the surface states have opposite effects on these parameters. Temperature dependence of the threshold voltage shows a linear decrease as the temperature increases. This trend is ascribed to the charge states at oxide/nanowire interfaces. Corners and surfaces of nanowire thus should play an important role for ultra-short nanowire transistors and that calls for shape of nanowire optimization for device design.