Effect of Process-Related Impurities on the Electrophysical Parameters of a MOS Transistor

Abstract

It is established that the electrophysical characteristics of MOS transistors largely depend on the quality of a gate dielectric. The presence of an extra built-in charge in the dielectric and fast surface states at the SiO2/Si interface leads to both an increased threshold voltage and decreased saturation current and voltage, decreased slopes of the characteristics of the MOS transistor in the linear and saturation regions, and a decreased structure conductance in the linear region. The gate leakage currents also increase. It is shown that the view and shape of the capacity–voltage characteristics are determined by the value of an extra positive charge in the bulk of the dielectric and the density of fast surface states at the Si/SiO2 interface. These values are correlated to the profile of the distribution of the surface concentration of the process-related impurities adsorbed at the wafer surface during the manufacturing of the device, which allows us to judge the quality of the materials used, adherence to the production conditions, and, if necessary, correct them opportunely as required.