Characteristics Of Field-effect Transistors Research Articles

Fabrication and Characterization of Self-Aligned WSe2 p-Type Field-Effect Transistor

Semiconducting transition metal dichalcogenides (TMDCs) have been growing interests as channel materials in field effect transistors (FET) for next generation low power digital electronics. [1]. Since a complementary metal oxide-semiconductor (CMOS) inverter constructed from pairs of n-type and p-type FETs is a fundamental building blocks in modern digital electronics [2], implementation of both n-type and p-type FETs with semiconducting TMDCs is of particular importance [3]. Among various semiconducting TMDCs, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [4]. These prominent features of WSe2 is suitable for an application to CMOS inverter.One of the significant challenges is to develop a top gate and top contact FET structure with WSe2 for CMOS device integration on the same wafer. In addition, it is desirable to minimize the access region between channel and S/D contact because this access region served as a series resistance to channel resistance, resulting in the lower drain current in FET. This study reports a self-aligned process to fabricate top gate and top contact WSe2 p-type FET. In this self-aligned structure, the gate electrode and source/drain contact edges are automatically positioned and hence there are no overlap or access region between the gate and source/drain. The feature of this proposed method is that the gate stacks was utilized as a mask for self-aligned formation of WOx, which is source/drain contact for efficient hole injection [5]. The focus on this study is the impact of self-aligned structure of p-type WSe2 FET on the electrical characteristics. The effectiveness of proposed process was experimentally demonstrated by the fabrication and characterization of device.Figures 1 shows the self-aligned fabrication process of p-type WSe2 FET. 20 nm-thick SiO2 was formed by dry oxidation of p+-Si substrate. The mechanically exfoliated multi-layer WSe2 was transferred by PDMS stamp. Next, 15 nm-thick Al2O3 was prepared by ALD at 200 oC with H2O. Then, Nickel (Ni) metal was deposited by RF sputtering on Al2O3. Ni metal was patterned for gate electrode with conventional lithography process. After that, A2O3 layer was removed by wet etching. Subsequently, substrate was exposed to oxygen radicals to form WOx used as source/drain contact at surface of WSe2. Second layer of Al2O3 was deposited as an encapsulating passivation layer. After the contact hole opening, the electrical contact pad was fabricated. Finally, forming gas (N2 : H2 = 97 % : 3 %) annealing was performed at 200 oC for 30 min. The top gate length was 5 μm. The gate width was estimated to be 40 μm by optical microscope. The electrical characteristics were measured with a manual probe station in an atmospheric pressure without inert gas purge at room temperature using a precision semiconductor parameter analyzer (Agilent 4156 C).Figures 2 shows the Id–Vg characteristics of fabricated FETs for (a) back gate operation and (b) top gate operation. Representative Id–Vg characteristics of p-type FETs were observed irrespective of back gate and top gate operation. The on/off ratio of about 106 ~ 107 order were obtained for both back gate and top gate operation. Furthermore, the threshold voltage and sub-threshold slope were modulated by varying the substrate bias during gate sweep.This study opens up interesting directions for the research and development of TMDC-based devices.AcknowledgmentsThis study was supported by a JSPS Grant-in-Aid for Scientific Research (C) (Grant No. 20K04616), a research grant for Tokyo Tech Challenging Research Award, the Samco Foundation and a research grant for Suematsu Award.

High Electric Field Transport Characteristics in Field-Effect Transistors Based on Monolayer/Few-Layer MoS2

In recent years, the high electric field transport characteristics in field-effect transistors (FETs) based on monolayer/few-layer molybdenum disulfide (MoS <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> ) have attracted much attention. However, as far as we know, there are no comprehensive and detailed reviews about the related investigations up to now. In this article, the recent advancements in numerical simulation and experimental investigation on the high electric field transport in monolayer/few-layer MoS <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> FETs will be analyzed, respectively. Then, several promising research directions, which may further improve the high electric field transport characteristics, are expounded. In addition, some important parasitic effect at a high electric field in monolayer/few-layer MoS <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> FETs, such as the self-heating effect, is introduced briefly. This article will provide meaningful guidance for the design of monolayer/few-layer MoS <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> FETs with higher performance at high electric fields in the future.

Si‐Doping Effects in AlGaN Channel Layer on Performance of N‐Polar AlGaN/AlN FETs

The nitrogen‐polar (N‐polar) AlGaN/AlN structure is expected to have higher carrier density than conventional metal‐polar AlGaN/GaN electronic devices, and the AlN substrate offers various advantages, such as high breakdown voltage and high‐temperature operation. Herein, a N‐polar AlGaN/AlN‐heterostructured field‐effect transistor (FET) with static FET characteristics is successfully fabricated. However, the drain current density, IDS, remains significantly small. This study aims to improve IDS by doping Si in the topmost AlGaN channel layer under various conditions.

Layer‐Dependent Optical Modulation and Field‐Effect‐Transistor in Two‐Dimensional 4H‐SnS2 Layers

AbstractTwo–dimensional (2D) 4H‐polytype tin disulfide (SnS2) flakes are synthesized using the chemical vapor transport technique. The weak Van der Waals force between the 2D SnS2 layers offers an easy exfoliation of flakes down to a bilayer of thickness ≈2.02 (±0.1) nm using a mechanical exfoliation technique. The optical and field effect transistor (FET) characteristics of the exfoliated 2D 4H‐SnS2 layers are studied. The exfoliated layers are used to fabricate the ≈13‐layered SnS2 FET. The 4H‐SnS2 exhibits a high on/off ratio of ≈106 and mobility ≈1–4 cm2 V−1 s−1. The low mobility of the 4H‐SnS2 FET devices shows an insulating state concordant with the 2D Motts variable range hopping mechanism at varying temperatures. Moreover, it is found that the optical bandgap of the 2D SnS2 single‐crystal layers is largely widened for the bilayers and tri‐layers. The optical bandgap energies vary in the range of 2.56–1.99 eV. The significant alteration in bandgap energies of ≈0.57 eV offers downscaling of the 2D nanoscale semiconducting devices. Such layer‐sensitive changes in optical transmittance, absorbance, and bandgap energies are reflected in Commission Internationale de L'Eclairage (CIE) chromaticity, showing the distinct color of transmittance through various 2D 4H‐SnS2 layers.

Modeling the Impact of Phonon Scattering with Strain Effects on the Electrical Properties of MoS2 Field-Effect Transistors.

Molybdenum disulfide (MoS2) has distinctive electronic and mechanical properties which make it a highly prospective material for use as a channel in upcoming nanoelectronic devices. An analytical modeling framework was used to investigate the I-V characteristics of field-effect transistors based on MoS2. The study begins by developing a ballistic current equation using a circuit model with two contacts. The transmission probability, which considers both the acoustic and optical mean free path, is then derived. Next, the effect of phonon scattering on the device was examined by including transmission probabilities into the ballistic current equation. According to the findings, the presence of phonon scattering caused a decrease of 43.7% in the ballistic current of the device at room temperature when L = 10 nm. The influence of phonon scattering became more prominent as the temperature increased. In addition, this study also considers the impact of strain on the device. It is reported that applying compressive strain could increase the phonon scattering current by 13.3% at L = 10 nm at room temperature, as evaluated in terms of the electrons' effective masses. However, the phonon scattering current decreased by 13.3% under the same condition due to the existence of tensile strain. Moreover, incorporating a high-k dielectric to mitigate the impact of scattering resulted in an even greater improvement in device performance. Specifically, at L = 6 nm, the ballistic current was surpassed by 58.4%. Furthermore, the study achieved SS = 68.2 mV/dec using Al2O3 and an on-off ratio of 7.75 × 104 using HfO2. Finally, the analytical results were validated with previous works, showing comparable agreement with the existing literature.

Improved Electrical Characteristics of Field Effect Transistors with GeSeTe-Based Ovonic Threshold Switching Devices.

Hyper-field effect transistors (hyper-FETs) are crucial in the development of low-power logic devices. With the increasing significance of power consumption and energy efficiency, conventional logic devices can no longer achieve the required performance and low-power operation. Next-generation logic devices are designed based on complementary metal-oxide-semiconductor circuits, and the subthreshold swing of existing metal-oxide semiconductor field effect transistors (MOSFETs) cannot be reduced below 60 mV/dec at room temperature owing to the thermionic carrier injection mechanism in the source region. Therefore, new devices must be developed to overcome these limitations. In this study, we present a novel threshold switch (TS) material, which can be applied to logic devices by employing ovonic threshold switch (OTS) materials, failure control of insulator-metal transition materials, and structural optimization. The proposed TS material is connected to a FET device to evaluate its performance. The results demonstrate that commercial transistors connected in series with GeSeTe-based OTS devices exhibit significantly lower subthreshold swing values, high on/off current ratios, and high durability of up to 108.

Direct Observation of Contact Reaction Induced Ion Migration and its Effect on Non-Ideal Charge Transport in Lead Triiodide Perovskite Field-Effect Transistors.

The migration of ionic defects and electrochemical reactions with metal electrodes remains one of the most important research challenges for organometal halide perovskite optoelectronic devices. There is still a lack of understanding of how the formation of mobile ionic defects impact charge carrier transport and operational device stability, particularly in perovskite field-effect transistors (FETs), which tend to exhibit anomalous device characteristics. Here, the evolution of the n-type FET characteristics of one of the most widely studied materials, Cs0.05 FA0.17 MA0.78 PbI3, is investigated during repeated measurement cycles as a function of different metal source-drain contacts and precursor stoichiometry. The channel current increases for high work function metals and decreases for low work function metals when multiple cycles of transfer characteristics are measured. The cycling behavior is also sensitive to the precursor stoichiometry. These metal/stoichiometry-dependent device non-idealities are correlated with the quenching of photoluminescence near the positively biased electrode. Based on elemental analysis using electron microscopy the observations can be understood by an n-type doping effect of metallic ions that are created by an electrochemical interaction at the metal-semiconductor interface and migrate into the channel. The findings improve the understanding of ion migration, contact reactions, and the origin of non-idealities in lead triiodide perovskite FETs.

Electronic and Charge Transport Properties in Bridged versus Unbridged Nanohoops: Role of the Nanohoop Size.

In the field of π-conjugated nanohoops, the size of the macrocycle has a strong impact on its structural characteristics, which in turn affect its electronic properties. In this work, we report the first experimental investigations linking the size of a nanohoop to its charge transport properties, a key property in organic electronics. We describe the synthesis and study of the first example of a cyclocarbazole possessing five constituting building units, namely [5]-cyclo-N-butyl-2,7-carbazole, [5]C-Bu-Cbz. By comparison with a shorter analogue, [4]-cyclo-N-butyl-2,7-carbazole, [4]C-Bu-Cbz, we detail the photophysical, electrochemical, morphological and charge transport properties, highlighting the key role played by the hoop size. In particular, we show that the saturated field effect mobility of [5]C-Bu-Cbz is four times higher than that of its smaller analogue [4]C-Bu-Cbz (4.22×10-5 vs 1.04×10-5 cm2 V-1 s-1 ). However, the study of the other organic field-effect transistor characteristics (threshold voltage VTH and subthreshold slope SS) suggest that a small nanohoop is beneficial for good organization of the molecules in thin films, whereas a large one increases the density of structural defects, and hence of traps for the charge carriers. The present findings are of interest for the further development of nanohoops in electronics.

Temperature Dependence of Electrical Characteristics of ZnO Nanowire Field-Effect Transistors with AZO and Aluminium Source/Drain Contact

In this study, ZnO nanowire field-effect transistor (FET) with an aluminium-doped ZnO (AZO) and an aluminium (Al) dual layer source and drain contact are fabricated and temperature dependent characteristics in the range of 200 – 300 K are analyzed through experimental measurements. The effect of temperature on threshold voltage, subthreshold slope, transconductance, and field effect mobility are analysed. The transfer curve exhibits a parallel shift toward a negative gate voltage direction with a negative shift of the threshold voltage, an increase in the subthreshold slope, and a field-effect mobility as the temperature rises. The electrical properties of the transistors demonstrate typical behaviour at various temperatures.

Simple Fabrication Method for Solution-gated One-piece Transistors for Biosensing Applications

In this paper, we report on a novel and simple fabrication method for solution-gated thin-film indium tin oxide (ITO) channel field-effect transistors (FETs). These devices can be fabricated by etching a part of deposited conductive ITO film with about 100 nm thickness to 20 nm thickness as the channel, which exhibits semiconductor characteristics. The current measurement during etching enables the direct observation of the change in current at the channel, that is, the precise optimization of FET characteristics. The devices fabricated show a steep subthreshold slope (~80 mV/decade) and a large I d/I g ratio; thus, they have the potential to be applied in highly sensitive affordable biosensors.

Largely Reducing the Contact Resistance of Molybdenum Ditelluride by In Situ Potassium Modification

AbstractSemiconducting molybdenum ditelluride (MoTe2) is widely reported owing to its favorable electronic and optoelectronic properties. The effective modulation of its electrical characteristics has garnered growing attention in regard to building high‐performance MoTe2‐based complementary devices. However, the inherent Schottky barrier (SB) in MoTe2‐based devices severely inhibits the charge‐carrier injection efficiency, leading to a high contact resistance between MoTe2 and contact metals. Here, an efficient method is presented for reducing the SB height of field‐effect transistors (FETs) based on MoTe2 by in situ potassium modification. Interestingly, the electrons transported from K continuously change the electrical characteristics of MoTe2 FET from ambipolar to n‐type with an improvement of electron mobility of over one order of magnitude. Meanwhile, the contact resistance of MoTe2 FET is significantly decreased from 11.5 to 0.4 kΩ µm. By regulating the modification region spatially, it is possible to create a complementary inverter with a high gain of ≈32 at VDD = 3 V. This research demonstrates a relatively simple method for optimizing the contact for MoTe2‐based devices and tuning the electrical properties of MoTe2 for future high‐performance complementary electronics.

Enhanced memory properties of HfO2-based ferroelectric capacitor by inserting Al2O3/ZrO2 stack interfacial layer

HfO2-based ferroelectrics have been regarded as a promising material to integrate into a gate stack of silicon-based field-effect-transistors (FETs). However, a narrower memory window (MW) and poor endurance caused by an undesirable interfacial layer (IL) impede the further adoption. In this study, the ferroelectric metal–oxide–semiconductor capacitor with high-k Al2O3/ZrO2 stack IL was constructed to optimize the memory characteristics. The robust MW of 1.64 V under a low operating voltage of ±2.5 V was achieved. In addition, the excellent endurance was demonstrated with an available MW of 1.10 V after 108 cycles. Such improvement is attributed to the surface passivation and seed effect by the inserted Al2O3 and ZrO2, respectively. The Al2O3/ZrO2 stack IL stabilizes the ferroelectric orthorhombic phase to enhance the MW and suppresses the charge trapping to improve the reliability. This work proposes an effective method to optimize the memory characteristics for ferroelectric FETs.

Tuning Dipole Orientation of 2,6-Azulene Units in Conjugated Copolymers by C–H Activation Strategy toward High-Performance Organic Semiconductor

Azulene has aroused widespread interest for constructing optoelectronic materials. However, controlling the dipole orientation of 2,6-azulene units in the conjugated polymer backbone is a significant challenge so far. Herein, by C-H activation strategy, three 2,6-azulene-TPD-based conjugated copolymers with different dipole arrangements were synthesized, where TPD = thieno[3,4-c]pyrrole-4,6-dione. The dipole arrangements of 2,6-azulene units were random for P(AzTPD-1), head-to-head/tail-to-tail for P(AzTPD-2), and head-to-tail for P(AzTPD-3). These polymers exhibited unipolar n-type semiconductor characteristics in organic field effect transistors. Moreover, regioregular polymer P(AzTPD-3) displayed the best device performance with an electron mobility of up to 0.33 cm2 V-1 s-1, which makes P(AzTPD-3) a high-performance n-type polymeric semiconductor. These results demonstrate that incorporation of 2,6-azulene units into the polymeric backbone together with the regulation of the dipole orientation of 2,6-azulene units is an effective strategy for obtaining high-performance organic optoelectronic materials.

Investigating the Mobility-Compressibility Properties of Conjugated Polymers by the Contact Film Transfer Method with Prestrain.

Up to now, researches on the mobility-stretchability of semiconducting polymers are extensively investigated, but little attention was paid to their morphology and field-effect transistor characteristics under compressive strains, which is equally crucial in wearable electronic applications. In this work, a contact film transfer method is applied to evaluate the mobility-compressibility properties of conjugated polymers. A series of isoindigo-bithiophene conjugated polymers with symmetric carbosilane side chains (P(SiSi)), siloxane-terminated alkyl side chains (P(SiOSiO)), and combined asymmetric side chains (P(SiOSi)) are investigated. Accordingly, a compressed elastomer slab is used to transfer and compress the polymer films by releasing prestrain, and the morphology and mobility evolutions of these polymers are tracked. It is found that P(SiOSi) outperforms the other symmetric polymers including P(Si─Si)andP(SiO─SiO), having the ability to dissipate strain with its shortened lamellar spacing and orthogonal chain alignment. Notably, the mechanical durability of P(SiOSi) is also enhanced after consecutive compress-release cycles. In addition, the contact film transfer technique is demonstrated to be applicable to investigate the compressibility of different semiconducting polymers. These results demonstrate a comprehensive approach to understand the mobility-compressibility properties of semiconducting polymers under tensile and compressive strains.

Comparative Study between Sulfurized MoS2 from Molybdenum and Molybdenum Trioxide Precursors for Thin-Film Device Applications.

Two-dimensional (2D) materials have been studied as an emerging class of nanomaterials owing to their attractive properties in nearly every field of science and technology. Molybdenum disulfide (MoS2) is one of the more promising candidates of these atomically thin 2D materials for its technological potential. The facile synthesis of MoS2 remains a matter of broad interest. In this study, MoS2 was synthesized by chemical vapor deposition sulfurization at various temperatures (550 °C, 650 °C, and 750 °C) of either precursor molybdenum metal (Mo) or molybdenum trioxide (MoO3) deposited on silicon/silicon dioxide (Si/SiO2) via e-beam evaporation. Monolayer, bilayer, and few layers sulfurized samples have been grown and verified by Raman, photoluminescence spectroscopy, XRD, XPS, and AFM. MoO3 sulfurization provided monolayer growth in comparison to Mo sulfurization under the same conditions and precursor thicknesses. Optical microscopy showed the homogeneous nature of grown samples. A main finding of this work is that MoO3 sulfurization produced higher quality MoS2 as compared to those grown by an Mo precursor. Device characteristics based on monolayer MoO3 sulfurized MoS2-x include nonvolatile resistive switching with Ion/Ioff ≈ 104 at a relatively low operating bias of ±1 V. In addition, field-effect transistor characteristics revealed p-type material growth with a carrier mobility ∼ 41 cm2 V-1 s-1, which is in contrast to typically observed n-type characteristics.

Effect of Hf x Zr1−x O2/Ge metal–ferroelectrics–insulator–semiconductor interfaces on polarization reversal behavior

To evaluate the polarization characteristics of ferroelectric-gate field-effect transistors, metal–ferroelectrics–insulator–semiconductor (MFIS) structures are often used. This study examines the influence of interface characteristics on polarization characterization in MFIS on low-impurity-concentration substrates by experimentally evaluating the ferroelectric properties of Hf x Zr1−x O2 (HZO)/Ge MFIS capacitors with different interface properties. Usually, polarization reversal behavior is not observed for MFIS capacitors on low-impurity-concentration substrates. However, it is found that, when the interface properties are poor and the interface state density is high, polarization reversal behavior can be observed even on the low-impurity concentration substrates. In lightly-doped MFIS capacitors with many interface states, the response of the interface states at low measurement frequencies suppresses the depletion layer change and voltage drop in the Ge substrate, resulting in the high electric field across the HZO films and observation of polarization reversal behavior.

Trap characteristics of hafnium oxide-based ferroelectric field-effect transistors measured by using a current transient method

The trap characteristics and polarization effect on the trapping behavior in Hf0.5Zr0.5O2 ferroelectric field-effect transistors were analyzed. The current transient that corresponds to the trapping/detrapping of charge carriers was measured and the exact time constant spectra were extracted. In accordance with the different time constants and activation energies as well as the dependence of the trapping behavior on the filling conditions, traps that originated from the oxygen vacancies in the Hf0.5Zr0.5O2 layer and from the Si/SiO2 interface trap states were identified. The detrapping peaks in time constant spectra showed a consistent changing trend with the variation of remanent polarization, confirming that the positive polarization enhanced the trapping of charge carriers injected from channel side to the ferroelectric layer.

Prediction of Device Characteristics of Feedback Field-Effect Transistors Using TCAD-Augmented Machine Learning

In this study, the device characteristics of silicon nanowire feedback field-effect transistors were predicted using technology computer-aided design (TCAD)-augmented machine learning (TCAD-ML). The full current-voltage (I-V) curves in forward and reverse voltage sweeps were predicted well, with high R-squared values of 0.9938 and 0.9953, respectively, by using random forest regression. Moreover, the TCAD-ML model provided high prediction accuracy not only for the full I-V curves but also for the important device features, such as the latch-up and latch-down voltages, saturation drain current, and memory window. Therefore, this study demonstrated that the TCAD-ML model can substantially reduce the computational time for device development compared with conventional simulation methods.

Effects of Charge Trapping on Memory Characteristics for HfO2-Based Ferroelectric Field Effect Transistors.

A full understanding of the impact of charge trapping on the memory window (MW) of HfO2-based ferroelectric field effect transistors (FeFETs) will permit the design of program and erase protocols, which will guide the application of these devices and maximize their useful life. The effects of charge trapping have been studied by changing the parameters of the applied program and erase pulses in a test sequence. With increasing the pulse amplitude and pulse width, the MW increases first and then decreases, a result attributed to the competition between charge trapping (CT) and ferroelectric switching (FS). This interaction between CT and FS is analyzed in detail using a single-pulse technique. In addition, the experimental data show that the conductance modulation characteristics are affected by the CT in the analog synaptic behavior of the FeFET. Finally, a theoretical investigation is performed in Sentaurus TCAD, providing a plausible explanation of the CT effect on the memory characteristics of the FeFET. This work is helpful to the study of the endurance fatigue process caused by the CT effect and to optimizing the analog synaptic behavior of the FeFET.

Thermal Sensing Characteristics of Low-Voltage n-Channel Organic Field-Effect Transistors With Triple Layers of Naphthalenediimide-Containing Conjugated Polymer and Gate-Insulating Polymers

Organic field-effect transistors (OFETs) were fabricated with n-type naphthalenediimide-based conjugated polymer (N2200) as a channel layer and poly(methyl methacrylate) (PMMA)/poly(vinyl alcohol) (PVA) as a gate-insulating layer. The OFETs with the N2200/PMMA/PVA triple layers were operated with an n-channel mode at low voltages (≤5 V) and their electron mobility reached ca. 0.63 cm2/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}\cdot \text{s}$ </tex-math></inline-formula> at a drain voltage of 5 V. The drain current of OFETs was gradually increased as the temperature of channel region increased from 25 °C to 80 °C, whereas no shift in threshold voltage was measured upon the temperature variation. The relative thermal sensitivity of devices was almost linearly increased with the temperature, while a two-stage behavior by a border of ca. 35 °C was measured for specific thermal sensitivity. The present n-channel OFETs exhibited excellent thermal sensing performances upon repeated approaching/retracting tests using a heat source.