Characteristics Of MOSFETs Research Articles

3-D Fully Coupled Electromagnetic Field Modeling and Characterization of SiC MOSFET Switching Transients

3-D Fully Coupled Electromagnetic Field Modeling and Characterization of SiC MOSFET Switching Transients

Degeneration mechanism of 30 MeV and 100 MeV proton irradiation effects on 1.2 kV SiC MOSFETs

In this study, we evaluated and characterized the effects of various proton irradiation energies and fluences on the electrical characteristics of SiC MOSFETs using a proton accelerator. The devices under test (DUTs) were fabricated utilizing 1.2 kV SiC MOSFET processes. To assess the impact of total ionizing dose (TID) and displacement damage (DD) on SiC MOSFETs, the DUTs were exposed to protons irradiation at energies of 30 MeV and 100 MeV, under ambient temperature conditions. Additionally, we examined the radiation hardness of DUTs under varying proton fluences, including 1 × 1012 cm−2, 1 × 1013 cm−2, 5 × 1013 cm−2, and 1 × 1014 cm−2.The results demonstrate that the threshold voltage (Vth) of the irradiated devices exhibited a negative shift, attributable to radiation-induced positive oxide trapped charges. This negative shift in Vth, coupled with the accumulation of positive trapped charges in the field limiting ring (FLR) oxide, resulted in augmented output currents and diminished breakdown voltage (BV) values. A significant reduction in current, ranging from 70% to 99%, was observed in the DUT subjected to irradiation at of 30 MeV and 1 × 1014 cm−2, highlighting the influence of DD. Conversely, irradiation at 100 MeV primarily revealed TID effects, characterized by a negatively shifted Vth. The on-state current at a gate voltage of 10 V and a drain voltage of 5 V of the DUT with irradiation of 100 MeV and 1 × 1014 cm−2 was a higher than that of DUT without irradiation because of a reduction of Vth.

Characteristics of silicon-based polycrystalline diamond MOSFETs prepared by three-step growth method

Hydrogen-terminated diamond (H-diamond) metal oxide field effect transistors (MOSFETs) were successfully fabricated on polished first-grown and unpolished secondary-grown silicon-based polycrystalline diamond films. The devices have a gate length of 8 μm, while an Al2O3 dielectric bilayer was deposited at 200 °C and 100 °C using atomic layer deposition (ALD). Compared to the first-grown diamond films with a root-mean-square roughness (Rq) of 257 nm, the films after polishing and subsequent second growth change the diamond growth mode, resulting in a mixed surface morphology characterized by faceted and step-bunching structures with a roughness (Rq) of 16.6 nm, and also leading to a decrease in grain boundary density and polishing-induced defects. Device analysis demonstrates that these changes result in an increase in the on/off ratio from 102 to 107 at a gate leakage current of 10−7 mA/mm. Meanwhile, although polished first-grown diamond films have atomic-level smoothness, the devices channels on unpolished secondary-grown diamond films show higher carrier concentration and mobility. The improvement in device performance indicates that the three-step growth method provides a new opportunity for the application of large-sized silicon-based polycrystalline diamond films in electronic devices.

The effect of temperature on the electrical characteristics of zigzag and armchair black phosphorus based 2D MOSFET

Abstract A first time comparative study of the thermal dependence of vital electrical characteristics of 2D MOSFETs based on black phosphorus for both zigzag and armchair orientations is presented in this paper. It is seen that a higher in-plane thermal conductivity in zigzag direction results in a much better on state current performance which comes at the cost of orders of magnitude increase in gate leakage and a reduced on to off state current ratio. The effect of temperature on threshold voltage (VTH), short channel effects like drain induced barrier lowering (DIBL), subthreshold swing (SS), Schottky barrier height ΦSB and transconductance behavior in both zigzag and armchair orientations is thoroughly discussed and the inherent physical mechanisms resulting the variations are also presented. Though increase in temperature is found to deteriorate the SS and drain conductance but at the same time, it is found to improve the short channel performance of the devices under consideration.

TCAD analysis of conditions for DIBL parameter misestimation in cryogenic MOSFETs

The study aimed to theoretically investigate the transfer characteristics of MOSFETs at cryogenic temperatures to elucidate the experimental conditions affecting the accurate estimation of the drain-induced barrier lowering (DIBL) parameter. Our Technology Computer Aided Design (TCAD) simulation revealed that MOSFETs featuring an underlap between the gate and source/drain edges experience a significant shift in threshold voltage (V t) in the low drain voltage (V d) region, which causes the misestimation of the DIBL parameter. This V t change is due to a notable increase in carrier concentration within the underlap region. To mitigate misestimation in such underlap devices, confirming the dependence of the DIBL parameter on the linear region of V d serves as an effective method to ensure accurate estimation.

Total Ionizing Dose (TID) Effects on the 1.2 kV SiC MOSFETs under Proton Irradiation

In this paper, the effects of various proton irradiation energies and doses on the electrical characteristics of SiC MOSFETs have been evaluated and characterized using a proton accelerator. The devices under test were designed, fabricated and packaged using 1.2 kV/0.6 µm-tech SiC MOSFET processes. The results demonstrate that the threshold voltage (Vth) of the irradiated devices shifted towards negative values due to the radiation-induced positive oxide trapped charges. Moreover, this negative shift in Vth and positive trapped charges of field limiting ring (FLR) oxide led to an increase in output currents and a reduction in the breakdown voltage values.

Junction temperature monitoring of silicon carbide MOSFET based on turn‐off voltage spike

AbstractBecause of the advantages of high switching speed, silicon carbide (SiC) devices are widely used in high‐power power electronic equipment. Real‐time monitoring of junction temperature is very important for the safe operation of equipment. There have been many studies on traditional junction temperature monitoring methods based on Si IGBT, but the dynamic characteristics of SiC MOSFETs are changed due to their different physical structure and parasitic parameters, which make the traditional methods no longer applicable. In this paper, the junction temperature can be extracted from the switching process of SiC MOSFET by using the turn‐off voltage spike as the index of thermosensitive electrical parameter (TSEP). In addition, the effect of working voltage, current, and different materials on turn‐off voltage spike is also studied. The simulation platform of Ansys/Simplorer and the experimental test platforms are built, and the theory of junction temperature detection based on turn‐off voltage spike is verified. The simulation and experimental results show that turn‐off voltage spike is a feasible TSEP, which can be used to extract junction temperature of SiC MOSFET with good linearity and instantaneity.

Study of Parasitic Effects for Accurate Dynamic Characterization of SiC MOSFEFTs: Comparison between Experimental Measurements and Numerical Simulations

The high-speed switching capabilities of wide bandgap (WBG) power devices have posed challenges in accurately evaluating their dynamic characteristics, primarily due to the increasing influence of parasitic components in switching test circuits. To address this issue, we investigated the impact of parasitics by conducting dynamic tests and schematic-level transient simulation on a half-bridge switching circuit incorporating SiC MOSFETs. This comparative analysis identified specific parasitic components responsible for undesirable behaviors such as spikes and ringing in the switching waveform. Our findings provide insights into which parasitic components in the test circuit are critical for the accurate dynamic characterization of SiC MOSFETs.

Improved Temperature-Scalable DC model for SiC power MOSFET including Quasi-Saturation effect

In this paper, accurate temperature-dependent static model for Silicon-Carbide (SiC) power MOSFET is presented. The proposed model is formed by two equations relating to linear and saturation operating regions. In this model, new formalism of the saturation drain current is introduced to consider the peculiar features observed in the I-V static characteristics of the SiC power MOSFET: a) moderate inversion region, or region of low gate voltages and b) quasi-saturation region, region of high gate voltages at which the drain current becomes less sensitive to the increase of gate voltage. In addition, the model captures with high-precision the transition region between linear and saturation region, pinch-off region, noticed in the output characteristics of the SiC power MOSFETs. It will be shown that the model equations ensure continuity and smooth transition between all operating regions. Temperature scaling of the model is carried out by its temperature scaling parameters. The proposed compact model is simple and efficient using reduced number of technology independent parameters. Simple parameter extraction procedure is described that uses an optimizer algorithm based on good experimental initial guess. Excellent agreement is obtained by comparing model to TCAD simulation and device measurement.

Neural-network-based transfer learning for predicting cryo-CMOS characteristics from small datasets

Transfer learning was examined to predict current-voltage (I-V) characteristics of MOSFETs at cryogenic temperatures. An experimental dataset was obtained from approximately 800 silicon-on-insulator MOSFETs using an automated cryogenic wafer prober to pre-train a 3-hidden-layer neural network (NN) model. Transfer learning based on the NN model was then conducted using another small dataset from 2 bulk MOSFETs. The transfer learning NN model predicted more realistic I-V characteristics and threshold voltages than a control NN model trained using only the small dataset. This study demonstrates cryogenic MOSFET characteristics prediction from a small dataset to reduce time and financial costs for developing cryo-CMOS devices.

Cryogenic Characteristics of MOSFET in Monolithic Silicon-Photonic Process

Cryogenic Characteristics of MOSFET in Monolithic Silicon-Photonic Process

Transient turn-on characteristics of Si RBDT and SiC MOSFET under nanosecond current pulse range

With the development of pulse power supplies, solid-state semiconductor switches are required to have fast switching speeds and low losses. Both Reverse blocking diode thyristor (RBDT) and silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) have fast turn-on speed, making them suitable candidates for short pulse generator. In this paper, the transient turn-on characteristics of Si RBDT and SiC MOSFET are analyzed theoretically and validated experimentally. Si RBDT and commercial 1.2 kV/81A SiC MOSFET are comparatively investigated in switching current pulse with a rise time of several hundreds of nanoseconds. (1) The anode current of RBDT could rise exponentially because of the latch-up effect of Si RBDT, while the drain current of SiC MOSFET tends to be saturated. (2) Utilizing the current rise time (Trise) to represent the switching speed, SiC MOSFET can switch faster when the current is lower than 400A. With the increase of the current, Si RBDT presents faster turn-on speed and lower switching loss due to the regenerative action of the two coupled transistors. (3) The transient characteristics of Si RBDT include a voltage-controlled inductance, while SiC MOSFET contains a current-controlled inductance based on the current rise time, respectively. With the increasing of the main voltage, the equivalent inductance of Si RBDT decreases and tends to be saturated when the main voltage is higher than half of the breakdown voltage of Si RBDT. For SiC MOSFET, the equivalent inductance increases until the drain current remains stable for a given gate voltage. This paper confirms the advantages of Si RBDT and SiC MOSFET in different situations.

Comparative Analysis of Single-Phase MOSFET-Based and IGBT-Based Inverters: A Performance Evaluation

his research paper explores the application of MOSFETs and IGBTs in the development of single-phase inverters. An Inverter is an electronic device or circuit that converts DC power into alternating current AC power. Commencing with an overview of inverters and their versatile applications, the study thoroughly examines the distinct characteristics of MOSFETs and IGBTs. It then provides detailed insights into the hands-on creation of single-phase inverters using these semiconductor components. Employing simulation tools, the study rigorously compares their efficiency, waveform quality, and responsiveness to dynamic changes. These findings contribute valuable information for selecting the most suitable semiconductor technology when designing practical and reliable single-phase inverters across a spectrum of applications.

Analyzing the Changes in the Third Quadrant Characteristics of SiC MOSFET Induced by Threshold Drift

Analyzing the Changes in the Third Quadrant Characteristics of SiC MOSFET Induced by Threshold Drift

MOSFET Characteristics and Related Biological Devices Analysis

With the development of modern electronic information technology, portable, fast, and high-performance electronic information products have brought great changes to people's life and health. People pay more and more attention to electronic information products. Not only in the civil aspect, high-end precision electronics industry, such as artificial intelligence, the new generation of electronic communication technology, medical devices, aerospace, and defense fields are based on various chips, to establish a complete national industrial system. This article describes MOSFET basic introduction, working principle and structure, etc., which plays an important role in the modern electronic information industry, including its application in implantable medical devices-current stimulator. The conclusion of this article is that with more and more capital and talent investment, the future of the chip industry with MOSEF as the basic component is very optimistic. The significance of this paper is to introduce the existing MOSFET technology and put forward views for future development.

The advantages and short circuit characteristics of SiC MOSFETs

SiC MOSFETs have exhibited considerable benefits in high-frequency, high-voltage, and high-temperature power electronics applications with outstanding material attributes as a result of the rapid advancement of power electronics technology. SiC MOSFETs slower short-circuit tolerance and faster switching rates provide new issues for the short-circuit prevention technology. In the opening section of the study, Si and SiC MOSFETs are compared and evaluated using various models and parametric factors. It has been demonstrated that SiC MOSFETs outperform Si MOSFETs in a variety of conditions and applications. The many SiC MOSFET short-circuit failure types as well as their underlying theories are initially explained in the papers main body. In addition, it examines the fundamentals of short-circuit test procedures and SiC MOSFET test circuits. The issues and limitations of the currently available SiC MOSFET short-circuit protection technology are then explored, along with factors impacting the short-circuit of SiC MOSFETs that are thoroughly examined. Lastly, the SiC MOSFET short-circuit protection technology development trend is forecasted, and potential future areas for improvement and innovation are considered. SiC MOSFET short-circuit protection technology will be enhanced and optimized to satisfy the needs of efficient and dependable power electronic systems as technology advances and application requirements expand.

Simulation study of trap-induced noise characteristics in FDSOI MOSFETs

The trap-induced noise characteristics of fully-depleted SOI (FDSOI) MOSFETs with ultra-thin body and buried oxide are essential for high-performance applications. However, accurate noise modeling and traps identification of the device remains challenging. In this work, we investigate the noise characteristics of FDSOI MOSFETs arising from traps in both the gate dielectric (GD) and the buried oxide (BOX). By using TCAD tool, we examine the noise generated by traps at various energy levels and spatial positions in GD and BOX under different biases. The simulation results reveal that traps in GD and BOX exhibit distinctly different behaviors as Vg increases, providing insights for identifying traps from noise measurement results.

An analytical subthreshold I–V model of SiC MOSFETs

In this article, an analytical I–V model for calculating subthreshold current of SiC MOSFETs is presented. This model starts with planar MOSFETs and utilizes the one-dimensional Poisson’s equation to derive an analytical expression for the surface potential. Subsequently, it employs this expression as a foundation for subthreshold current calculations. Then the model is extended to DMOSFETs based on the fact that channel current formation mechanism of DMOSFETs is similar to that of planar MOSFETs. Comparative analysis of our model calculations with two-dimensional numerical simulation software reveals that our model exhibits a high degree of agreement in the case of planar MOSFETs and DMOSFETs. Interface traps were also considered in our analytical model, which agrees well with experimental data published elsewhere. Furthermore, the model retains a certain degree of accuracy and predictive capability even in the presence of short-channel effect. Our subthreshold model becomes complementary to existing models which only describe the I–V characteristics of SiC MOSFETs when the transistors operate above the threshold voltages.

Applications and challenges of Silicon Carbide (SiC) MOSFET technology in electric vehicle propulsion systems: A review

Silicon Carbide (SiC) MOSFET technology plays a pivotal role in the drive systems of electric vehicles (EVs), offering key applications and facing significant challenges. This paper provides an overview of the fundamental principles and characteristics of SiC MOSFETs, highlighting the unique properties of SiC materials. It delves into the critical applications of SiC MOSFETs in electric vehicle drive systems, including motor drives and inverters, and analyzes the advantages of using SiC MOSFETs for efficient energy conversion at high temperatures. The paper also discusses the key challenges faced by SiC MOSFET technology, such as stability issues under high-temperature environments, avalanche breakdown and tolerance issues affecting power supply reliability, and manufacturing cost and consistency issues that limit widespread application. Innovative solutions to these challenges are explored, including strategies for improving stability under high temperatures, techniques for suppressing avalanche effects and enhancing power supply reliability, and innovations in manufacturing processes to reduce costs and improve consistency. The paper concludes by summarizing the crucial role of SiC MOSFET technology in electric vehicle drive systems, emphasizing the importance of innovative solutions to address its challenges, and looking forward to its continued contribution to technological advancements in the field of electric vehicles.

Enhanced gate biasing resilience in asymmetric and double trench SiC MOSFETs towards generalized highly reliable power electronics

The gate oxide quality in SiC MOSFETs presents a significant challenge, particularly at temperatures exceeding 175 °C. This predicament arises from the gate oxide interface's propensity to trap or release charge carriers, compromising device ruggedness. In mainstream SiC MOSFETs, the gate oxide in the trench corner confronts the demanding task of enduring higher electric field strengths, thereby posing a substantial risk to overall device reliability. As a result, research entities are proactively involved in improving the SiC/oxide interfaces to enhance the devices' resilience against elevated E-field. This endeavor aims to maintain the favorable characteristics of the trench SiC MOSFETs, including low on-state resistance, minimal parasitic capacitance, and exceptional switching performance. Thus, the implementation of a streamlined process becomes crucial to fortify the trench corner, ultimately yielding boosted E-field immunity. In this report, our research focuses on enhancing the reliability of trench corner in SiC MOSFET devices. Specifically, we employ spacer etch technology to selectively shield the trench corner with high-K heterolayers, thereby enhancing the device's ability to withstand higher E-field strengths (59.2 % reinforcement) while mitigating the risk of hidden defects. Importantly, compared to the structure without protection, at high-K shielded layer contact angles ranging from 90 to 150°, the E-field decreases, correlated the enhanced reinforcement at larger angles. Furthermore, such technology enables higher E-fields and greater circuit capacity at the bottom of trench gate, leading to enhanced device reliability. Our studies confirm that the developed device structure exhibits simplicity, reliability, maturity, and controllability, rendering it suitable for large-scale integration applications.