Channel Mismatch Research Articles

Deep transfer learning for improving single-EEG arousal detection.

Datasets in sleep science present challenges for machine learning algorithms due to differences in recording setups across clinics. We investigate two deep transfer learning strategies for overcoming the channel mismatch problem for cases where two datasets do not contain exactly the same setup leading to degraded performance in single-EEG models. Specifically, we train a baseline model on multivariate polysomnography data and subsequently replace the first two layers to prepare the architecture for single-channel electroencephalography data. Using a fine-tuning strategy, our model yields similar performance to the baseline model (F1=0.682 and F1=0.694, respectively), and was significantly better than a comparable single-channel model. Our results are promising for researchers working with small databases who wish to use deep learning models pre-trained on larger databases.

Single-Channel LCMV-Based Adaptive Beamforming With Time-Modulated Array

A novel single-channel linearly constrained minimum variance (LCMV)-based adaptive beamforming method with time-modulated array is proposed and verified. Time-modulated technique is utilized to generate a modulated single-channel signal. Furthermore, in digital domain, with $l_2$ norm optimization, covariance matrix of original signal is recovered from the sideband signals, which are extracted from the single-channel signal. Finally, the optimal weighting vectors can be determined by LCMV. The proposed method has lower channel mismatches, hardware complexity, and cost compared to the traditional multichannel structure. And in the procedure, only fixed time sequences are needed to calculate the weights and obtain the output signal. Simulation results are provided to show the procedure and verify its effectiveness.

High Precision Pseudo-Range Measurement in GNSS Anti-Jamming Antenna Array Processing

Radio frequency interference has become a rising problem to the signal of the Global Navigation Satellite System (GNSS). An effective way to achieve anti-jamming is by using an antenna array in GNSS signal processing. However, antenna array processing will cause a decline in the accuracy of pseudo-range measurements because of the channel mismatch and some other non-ideal factors. To solve this problem, space–time or space–frequency adaptive array processing is widely used for interference cancellation while constraining the delay of each antenna at the same time. In this paper, an anti-jamming algorithm with a time-delay constraint is proposed, where one antenna is chosen as the reference and data from other antennas is corrected based on the signal received from it. The deduction and simulation results show that the proposed algorithm can effectively improve the accuracy of pseudo-range measurements without degradation of anti-jamming performance.

An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

The time-interleaved analog-to-digital converters (TIADCs), performance is seriously affected by channel mismatches, especially for the applications in the next-generation communication systems. This work presents an improved all-digital background calibration technique for TIADCs by combining the Hadamard transform for calibrating gain and timing mismatches and averaging for offset mismatch cancellation. The numerical simulation results show that the proposed calibration technique completely suppresses the spurious images due to the channel mismatches at the output spectrum, which increases the spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) by 74 dB and 43.7 dB, respectively. Furthermore, the hardware co-simulation on the field programmable gate array (FPGA) platform is performed to confirm the effectiveness of the proposed calibration technique. The simulation and experimental results clarify the improvement of the proposed calibration technique in the TIADC’s performance.

A 5-GS/s 7.2-ENOB Time-Interleaved VCO-Based ADC Achieving 30.5 fJ/cs

This article presents an eight-channel time-interleaved voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC), achieving 7.2 effective number of bits (ENOBs) at 5 GS/s in 28-nm CMOS. A high-speed ring oscillator with feedforward cross-coupling and a shared tail transistor is combined with an asynchronous counter in order to improve the resolution while minimizing the power consumption. Asynchronous double sampling is used to enable reliable sampling of the asynchronous counter state. On-chip digital calibration is used to compensate for channel mismatch and nonlinear distortion, and sampling time mismatch is corrected using tunable clock delays. With a total power consumption of just 22.7 mW, it achieves a Walden figure-of-merit (FOM) of 30.5 fJ/cs.

Low computing resource consumption fully digital foreground calibration technique for time-interleaved analog-to-digital converter

A time-interleaved analog-to-digital converter (TI-ADC) uses several sub-analog-to-digital converters (sub-ADCs) to achieve a high sampling rate. Its applications include communication systems, oscilloscopes, healthcare instruments, etc. However, the presence of sub-ADC channel mismatches such as offset, gain and sample-time mismatches can significantly degrade the performance of TI-ADCs. This paper proposes a fully digital foreground calibration technique for the TI-ADC, including mismatch correction and estimation blocks. Unlike existing techniques, the proposed technique requires low computational resources. As the resource for complex computing in a field-programmable gate array (FPGA) is mainly the digital signal processor (DSP), the mismatch correction block unifies each computing unit in the FPGA into a multiply adder to achieve low DSP consumption. To further reduce the use of DSP resources, the selection of an optimal number of taps of the finite impulse response filter used for mismatch correction is discussed. The optimal-tap filter that uses the lowest amount of DSPs while satisfying the required signal-to-noise and distortion ratio flat area bandwidth is presented. A real-time hardware correction block was implemented for an 8 Gs/s TI-ADC system with two sub-ADC channels, and the results with this hardware verify the low computing resource consumption feature of the proposed calibration technique.

Dynamic Threshold Detection Using Clustering in the Presence of Channel Mismatch and Additive Noise

We report on the feasibility of k-means clustering techniques for the dynamic threshold detection of encoded q-ary symbols transmitted over a noisy channel with partially unknown channel parameters. We first assess the performance of k-means clustering technique without dedicated constrained coding. We apply constrained codes which allows a wider range of channel uncertainties so improving the detection reliability.

An Improved Airborne Multichannel SAR Imaging Method With Motion Compensation and Range-Variant Channel Mismatch Correction

To obtain a high-resolution and wide-swath image, the azimuth multichannel technique has been widely used in synthetic aperture radar (SAR) systems to overcome the contradiction between the wide swath and high pulse repetition frequency. For a high image quality, channel mismatch correction is an essential step in the multichannel SAR data imaging. However, in the case of airborne multichannel SAR, motion errors will severely degrade the performance of channel mismatch correction. To deal with this problem, this article proposes an improved airborne multichannel SAR imaging method with motion compensation, and range-variant channel mismatch correction. First, motion errors are compensated based on resampling and phase compensation. Then, the time-delay and constant gain-phase errors between channels are estimated and corrected, followed by the range-variant phase error correction based on a novel range-down-sampling method, which reduces the influence of motion errors on the channel mismatch correction significantly. Finally, simulated and real data processing results are used to demonstrate the effectiveness of the proposed method.

On Cross-Corpus Generalization of Deep Learning Based Speech Enhancement.

In recent years, supervised approaches using deep neural networks (DNNs) have become the mainstream for speech enhancement. It has been established that DNNs generalize well to untrained noises and speakers if trained using a large number of noises and speakers. However, we find that DNNs fail to generalize to new speech corpora in low signal-to-noise ratio (SNR) conditions. In this work, we establish that the lack of generalization is mainly due to the channel mismatch, i.e. different recording conditions between the trained and untrained corpus. Additionally, we observe that traditional channel normalization techniques are not effective in improving cross-corpus generalization. Further, we evaluate publicly available datasets that are promising for generalization. We find one particular corpus to be significantly better than others. Finally, we find that using a smaller frame shift in short-time processing of speech can significantly improve cross-corpus generalization. The proposed techniques to address cross-corpus generalization include channel normalization, better training corpus, and smaller frame shift in short-time Fourier transform (STFT). These techniques together improve the objective intelligibility and quality scores on untrained corpora significantly.

A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step.

Analysis of TIADC channel mismatch effects on high-resolution range profile

Analysis of TIADC channel mismatch effects on high-resolution range profile

Channel equalisation method for wideband digital array radar

In the radar systems, such as frequency source, power amplifier, mixer, filter and A/D converter, ageing devices, temperature and environmental changes etc., it is inevitable to introduce wideband amplitude/phase error. These can cause seriously channel mismatch that will affect the performance of digital beam-forming, synthetic aperture radar image, space time adaptive processing (STAP), automatic target recognition (ATR), target detection, clutter/interference suppression, pulse compression results and cancellation ratio etc. So this study mainly discusses that the channel amplitude/phase inconsistency of wideband digital array radar affects the pulse compression, beam forming and so forth. It also researches and analyses channel equalisation method, and the simulation and experimental results based on the experimental data show that the method based on Fourier transform is effectively and convenient. The Fourier transform method is easier for hardware implementation that can be applied to practical engineering.

GMTI STAP performance under space‐time impaired clutter environment

Ground moving target indicator (GMTI) RADAR system frequently incorporates space-time adaptive processing for successful moving targets discrimination in a highly cluttered environment. The minimum detectable velocity (MDV) of the target gets affected due to the added clutter impairments such as foliage penetration and angle independent channel mismatch. A novel clutter model is postulated in this work that includes assessment enacted in view of both angle and Doppler clutter impairments at a time instead of their individual analysis as in the reported literature. The performance of the GMTI RADAR in terms of the signal-to-interference-plus-noise ratio loss is evaluated using the extrusive beamforming methods namely sample matrix inversion and principal component canceller. In high decorrelated clutter environment, the later outperforms in terms of the MDV, making use of a lesser number of training snapshots. The approach is validated with mathematical modelling and numerical simulations.

An Interleaved Broadband Photonic ADC Immune to Channel Mismatches Capable for High-Speed Radar Imaging

A dual channel interleaved broadband subsampling photonic analog-to-digital converter (ADC) immune to channel mismatches capable for high-speed radar imaging is presented. Through modeling as a combination of photonic subsampling front-end and interleaved Nyquist sampling electronic ADC back-end, the mechanism of photonic interleaved subsampling of broadband signal and the appearance of spurious components caused by channel mismatches are explained. The effect of these spurious components on radar detecting is revealed. Through fractional Fourier domain filtering, the spurious components are eliminated, making the SNR of received X-band chirp signal (8–11.9 GHz) improved from 13.26 to 23.88 dB. Thanks to its downsampling and interleaved architecture, the demands of bandwidth, sampling rate, and storage depth for post electronics are all lowered, making it capable for high-speed and mass data receiving. In the experiment, inverse synthetic aperture radar imaging is performed characterized with range and cross range resolution of 4.9 and 7.9 cm. The false target due to the spurious component is distinguished through band-pass filtering in matched fractional Fourier domain.

A 3-mW 12b 160-MS/s 2-Way Time-Interleaved Subrange SAR ADC in 65-nm CMOS

This brief presents a 12-bit 2-way time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). This brief applied the master clock sampling and gain/offset correction schemes to mitigate channel mismatch errors. In the channel ADC, the subrange SAR ADC architecture was used to maintain high-speed and low-power features. A common bootstrapping circuit was proposed for suppressing the sampling error between coarse and fine ADCs. An intrinsic random sequence was applied to the capacitor swapping. The prototype ADC was fabricated using 65-nm CMOS technology, and it consumed 3 mW from a 1.2-V supply at a sampling rate of 160-MS/s. The measured peak signal-to-noise ratio and spurious-free dynamic range were 60.5 and 80 dB, respectively. The measured peak effective number of bits was 9.76, which is equivalent to a figure-of-merit of 21.6 fJ/conversion-step.

A 12.1 fJ/Conv.-Step 12b 140 MS/s 28-nm CMOS Pipelined SAR ADC Based on Energy-Efficient Switching and Shared Ring Amplifier

This brief presents an ultra-low-power two-channel 12b 140 MS/s 28-nm CMOS analog-to-digital converter (ADC) for use in next-generation mobile communications systems. The proposed ADC employs a two-stage pipelined successive-approximation register (SAR) ADC architecture, where the SAR ADC at each stage determines 5b and 8b, respectively. In the first-stage 5b SAR ADC, the switching power consumption is significantly reduced due to the switching operation by only a separate digital-to-analog converter (DAC) with a small unit capacitance, which generates the comparator decision threshold. When this setup is applied to an actual system, the reference voltage driver of the system is less burdened. Furthermore, the SAR ADC employs a custom-encapsulated capacitor to improve the limited linearity of a DAC caused by parasitic capacitance. A residue amplifier employs an ultra-low power ring amplifier structure. The amplifier is shared by each channel to reduce not only the power consumption and die area but also channel mismatches. The prototype ADC in a 28-nm CMOS process demonstrates a measured differential non-linearity and integral non-linearity within 1.50 LSB and 2.85 LSB at 12b, respectively, with a maximum signal-to-noise-and-distortion ratio and a spurious-free dynamic range of 58.0 dB and 73.7 dB at 140 MS/s, respectively. The ADC occupies an active die area of 0.202 mm2 and consumes 1.1 mW at a 0.8-V supply voltage, corresponding to a figure of merit of 12.1 fJ/conversion-step.

Analysis and Correction of Combined Channel Mismatch Effects in Frequency-Interleaved ADCs

In this paper, a comprehensive system behavioral model of frequency-interleaved analog-to-digital converters (FI-ADCs) is presented. The model addresses mismatch errors due to imperfect channel separation, incomplete anti-aliasing, in-phase/quadrature branch imbalances, and jitter-induced distortions. Using this model, an integrated analysis of combined channel mismatch effects is provided. Given error parameters or their distributions, closed-form expressions of the expected output signal-to-noise ratio and image rejection ratio are formulated for FI-ADCs with an arbitrary number of channels. The inherent circuit behaviors, sampling clock jitters, and local oscillator phase noise effects are also discussed. Based on the analysis and modeling, a discrete-time equivalent model for FI-ADC systems is derived. Therefrom, an integrated channel mismatch compensation scheme is proposed that contrasts existing signal recovery approaches which calibrate specific types of errors separately. The performance of this novel method is compared with conventional solutions using extensive simulations. Very favorable numerical results are observed.

Robust Radial Velocity Estimation Based on Joint-Pixel Normalized Sample Covariance Matrix and Shift Vector for Moving Targets

The clutter suppression and target radial velocity estimation are essential in the ground moving target indication processing with multichannel synthetic aperture radar (SAR) systems. In reality, the heterogeneous clutter, the image coregistration error, and channel mismatch will remarkably decline the estimation performance of the target radial velocity. To address these issues, a robust radial velocity estimation algorithm is proposed in this letter. Based on the joint-pixel signal model, the joint-pixel normalized sample covariance matrix (JPNSCM) is employed to mitigate the effect of heterogeneous clutter, and the shift vector determined by JPNSCM is used to obtain the actual target steering vector. Then, the adaptive matched filtering algorithm is adopted to estimate the target radial velocity. Compared with traditional estimation algorithms, the proposed method obtains better performance in both simulations and real SAR data experiments.

An adaptive calibration technique of timing skew mismatch in time-interleaved analog-to-digital converters.

Because of the exponential increase of sampling rate, time-interleaved analog-to-digital converter (TIADC) has a fast growth in the high-speed applications. However, the channel mismatch error is a serious challenge for the performance of TIADC. In this article, we address the timing skew mismatch error and propose a novel adaptive calibration method. The principle and operating process of the calibration algorithm are explained. To validate the proposed technique, we designed a four-channel TIADC-based digital oscilloscope with a sampling rate of 10 GS/s. Based on this instrumentation platform, (i) calibration algorithm was implemented by hardware; and (ii) a test platform consisting of advanced instruments and tools was setup to testify the effect and robustness of proposed algorithm. Moreover, the technical details of instrumentation are described for the first time. The experimental results show that the calibration algorithm significantly suppresses the distortions due to timing skew mismatch error. The TIADC-based instrumentation achieves spurious-free dynamic range of 52.48 dB and effective number of bits of 5.83 bit, respectively. Besides, the complexity of the proposed algorithm is compared and discussed.

Automatic Calibration Method of Channel Mismatches for Wideband TI-ADC System

Time-interleaved analog-to-digital converter (TI-ADC) technology can increase the sampling rate without changing resolution. But, the dynamic performance of TI-ADC system is seriously deteriorated by channel mismatches. Under the condition of large bandwidth, gain mismatch and timing mismatch vary with the frequency, which cannot be regarded as fixed values. To improve the dynamic performance of the TI-ADC system, an automatic calibration method of channel mismatches for wideband TI-ADC system is proposed in this article. Frequency-dependent channel mismatches are estimated by the algorithm based on sine fitting, and compensated by the means based on perfect reconstruction. The entire sampling and calculation process is automated and tedious operation is simplified. A 6.8-GS/s 12-bit wideband TI-ADC system is implemented. This sampling system can achieve SNDR (signal-to-noise and distortion ratio) above 49 dB and SFDR (spurious-free dynamic range) above 57 dB for an input signal from 100 MHz to 3300 MHz. The proposed calibration method improves the SNDR over 10 dB and the SFDR over 15 dB. The dynamic performance of the sampling system is close to that of its sub-ADC.