A 3-mW 12b 160-MS/s 2-Way Time-Interleaved Subrange SAR ADC in 65-nm CMOS

Abstract

This brief presents a 12-bit 2-way time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). This brief applied the master clock sampling and gain/offset correction schemes to mitigate channel mismatch errors. In the channel ADC, the subrange SAR ADC architecture was used to maintain high-speed and low-power features. A common bootstrapping circuit was proposed for suppressing the sampling error between coarse and fine ADCs. An intrinsic random sequence was applied to the capacitor swapping. The prototype ADC was fabricated using 65-nm CMOS technology, and it consumed 3 mW from a 1.2-V supply at a sampling rate of 160-MS/s. The measured peak signal-to-noise ratio and spurious-free dynamic range were 60.5 and 80 dB, respectively. The measured peak effective number of bits was 9.76, which is equivalent to a figure-of-merit of 21.6 fJ/conversion-step.