A 5-GS/s 7.2-ENOB Time-Interleaved VCO-Based ADC Achieving 30.5 fJ/cs

Abstract

This article presents an eight-channel time-interleaved voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC), achieving 7.2 effective number of bits (ENOBs) at 5 GS/s in 28-nm CMOS. A high-speed ring oscillator with feedforward cross-coupling and a shared tail transistor is combined with an asynchronous counter in order to improve the resolution while minimizing the power consumption. Asynchronous double sampling is used to enable reliable sampling of the asynchronous counter state. On-chip digital calibration is used to compensate for channel mismatch and nonlinear distortion, and sampling time mismatch is corrected using tunable clock delays. With a total power consumption of just 22.7 mW, it achieves a Walden figure-of-merit (FOM) of 30.5 fJ/cs.