Channel Length Modulation Effect Research Articles

Two-Dimensional Analytical Drain Current Model for Double-Gate MOSFET Incorporating Dielectric Pocket

In this paper, a dielectric-pocket double-gate MOSFET is described for low-voltage low-power applications. A complete drain current model has been developed including the channel length modulation effect. The analytical results have been validated by comparing them with the simulation results using the ATLAS 3-D device simulator. This paper analyzes the impact of dielectric pillars on large-signal performance metrics in terms of linearity and digital performance. Due to high <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio, device gain, and extremely low value of intrinsic delay and power dissipation, the proposed design is a suitable candidate for low-voltage low-power digital and analog applications.

Delay analysis of UDSM CMOS VLSI circuits

Propagation delay is one of the important issues for designing and synthesizing any VLSI circuits. In this paper, a simple and accurate delay model has been developed for Ultra Deep Sub-Micron (UDSM) CMOS inverter based on nth power law of MOSFET model when the channel length is in the order of less than or equal to 90nm. Modified model is also applied in the CMOS NANAD2 and CMOS NOR2 in the UDSM range. All the parameters are extracted from BSIM.4.6.1 MOSFET user manual. This work derives analytical expression for the delay model of a CMOS inverter including all sorts of secondary effects such as Body Bias effect, Channel Length Modulation effect (CLM), Velocity Saturation effect, Drain Induced Barrier Lowering (DIBL), Gate Induced Drain Leakage (GIDL), etc which may be occurred in the UDSM MOS devices. Our result is better than nth power law and simulation results with respect to propagation delay time. Our proposed model gives an average error of 3.78% & 6.9% with compare to Cadence & Tanner Simulation results respectively.

The influence of channel length on total ionizing dose effect in deep submicron technologies

The influence of channel length on total ionizing dose effect in a 180 nm complementary metal-oxide semiconductor technology is studied. When other conditions such as radiation bias, device structure are the same, the overall radiation response is determined by the charges trapped in the oxide. The off-state leakage due to the charges trapped in the shallow trench isolation oxide inverting the parasitic sidewall channel has correlation with the channel length. A shorter channel leads to a larger leakage current. For the first time, we report that the leakage current also exhibits the radiation enhanced channel-length modulation effect, which further degrades the device performance.

Symmetrical unified compact model of short-channel double-gate MOSFETs

An explicit charge-based unified compact drain current model for lightly doped or undoped DG MOSFETs is proposed. It takes into account the short-channel effects, the subthreshold slope degradation, the drain-induced barrier lowering and the channel length modulation effects. The model is valid and continuous in all regimes of operation and it has been validated by developing a Verilog-A code and comparing the model results of transfer and output characteristics with simulation results exhibiting an average error of about 3%. The efficient solution of the Lambert W function for the inversion charge and the symmetry of the model make it suitable for circuit simulation and allow fast and accurate simulations of the transistor characteristics.

Analytical I–V model of SOI and SON MOSFETs: a comparative analysis

A generalised three-interface compact capacitive threshold voltage model for horizontal silicon-on-insulator/silicon-on-nothing (SOI/SON) MOSFET has been developed. The model includes different threshold voltage-modifying short-channel phenomena like fringing field, junction-induced 2D-effects, etc. Based on the threshold voltage model, an analytical current voltage model is formulated from the basic charge control analysis of MOSFET. In order to provide a better explanation to various observations and applicable to short-channel SOI and SON structures, the present current voltage model includes the effect of carrier velocity saturation and channel length modulation. Identical structures for both the devices, SOI and SON, are considered but for SON MOSFET, the buried oxide layer is replaced by air. The performance of the two devices are studied and compared in terms of threshold voltage roll-off, subthreshold slope, drain current and drain conductance. The SON MOSFET technology is found to offer devices with further scalability and enhanced performance in terms of threshold voltage roll-off, sub-threshold slope and greater current derivability, thereby providing scope for further miniaturisation of devices and much better performance improvement.

Linearity-Distortion Analysis of GME-TRC MOSFET for High Performance and Wireless Applications

In this present paper, a comprehensive drain current model incorporating the effects of channel length modulation has been presented for multi-layered gate material engineered trapezoidal recessed channel (MLGME-TRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: gm<SUB>1</SUB>, gm<SUB>2</SUB>, gm<SUB>3</SUB>, and figure-of-merit (FOM) metrics; V<SUB>IP2</SUB>, V<SUB>IP3</SUB>, IIP3 and I-dB compression point, has been obtained. It is shown that, the incorporation of multi-layered architecture on gate material engineered trapezoidal recessed channel (GME-TRC) MOSFET leads to improved linearity performance in comparison to its conventional counterparts trapezoidal recessed channel (TRC) and rectangular recessed channel (RRC) MOSFETs, proving its efficiency for low-noise applications and future ULSI production. The impact of various structural parameters such as variation of work function, substrate doping and source/drain junction depth (X<SUB>j</SUB>) or negative junction depth (NJD) have been examined for GME- TRC MOSFET and compared its effectiveness with MLGME-TRC MOSFET. The results obtained from proposed model are verified with simulated and experimental results. A good agreement between the results is obtained, thus validating the model.

A 4T Low-Power Linear-Output Current-Mediated CMOS Image Sensor

In this paper, we present a 4T low-power linear output current-mediated CMOS APS imager, in which reset and read-out operations are carried-out simultaneously on two pixels of the same row. The proposed operating technique greatly simplifies the pixel architecture with only four transistors and two control signals required, while six transistors and four control lines are required by its current-mediated counterpart. The imager achieves fixed pattern noise (FPN) correction during pixel-readout and exhibits a power consumption which is independent of the imager array size, since only a single current source is solicited at any given time due to the array-level operating technique. A linearization circuit technique using the transistor's channel length modulation effect is employed enabling to double the linear range of the pixel's photon-to-output signal transfer function. Performance analysis and experimental results are presented for a 32 × 32 image sensor array prototype, fabricated using AMS 0.35-μm process. The pixel size is 6.5 × 6.5 μm2 with 22% fill-factor. The chip total power consumption is less than 1 mW, at 50 frames/s with a 3.3 V power supply.

A 1-V, 16.9 ppm/$^{\circ}$C, 250 nA Switched-Capacitor CMOS Voltage Reference

An ultra low-power, precise voltage reference using a switched-capacitor technique in 0.35-μm CMOS is presented in this paper. The temperature dependence of the carrier mobility and channel length modulation effect can be effectively minimized by using 3.3 and 5 V N-type transistors to operate in the saturation and subthreshold regions, respectively. In place of resistors, a precise reference voltage with flexible trimming capability is achieved by using capacitors. When the supply voltage is 1 V and the temperature is 80°C, the supply current is 250 nA. The line sensitivity is 0.76%/V; the PSRR is -41 dB at 100 Hz and -17 dB at 10 MHz. Moreover, the occupied die area is 0.049 mm2.

Analytical Drain Current Modeling of Dual-Material Surrounding-Gate MOSFETs

The asymmetrical halo and dual-material gate structure is used in the surrounding-gate metal-oxide-semiconductor field effect transistor (MOSFET) to improve the performance. By treating the device as three surrounding-gate MOSFETs connected in series and maintaining current continuity, a comprehensive drain current model is developed for it. The model incorporates not only channel length modulation and impact ionization effects, but also the influence of doping concentration and vertical electric field distributions. It is concluded that the device exhibits increased current drivability and improved hot carrier reliability. The derived analytical model is verified with numerical simulation.

Nonsaturating Drain Current Characteristic in Short-Channel Amorphous-Silicon Thin-Film Transistors

Nonsaturating drain current characteristics are analyzed in terms of the channel length modulation (CLM) and the self-heating effect. According to this analysis, the nonsaturating drain current arises if the effective channel length is sufficiently reduced such that the CLM effect leads to a superlinear increase of the drain current beyond saturation. The extracted CLM parameter was around ?' = 1/15 ?m/V for the samples investigated, and a nonsaturating characteristic was observed in hydrogenated-amorphous-silicon (a-Si:H) thin-film transistors (TFTs) with a channel length of 10 ?m or less. Furthermore, in a bias-temperature-stressed short-channel a-Si:H TFT, which has a laterally nonuniform threshold voltage, the experimental data showed a pronounced nonsaturating current in the reverse output characteristics and a much lower and flatter characteristic in the forwardId-Vds data. The nearly flat forward saturation characteristic is discussed in terms of the cancellation of the CLM effect by the effect from the rising threshold voltage at the pinchoff point as the drain bias increases. The pronounced nonsaturating reverse characteristic is explained in terms of the compounding effects of the rising CLM current and the rising current due to the falling threshold voltage of the pinchoff point. We also discuss a split-channel design to suppress the nonsaturating drain currents in a-Si:H TFTs.

Nano Scale Soi Mosfet Structures and Study of Performance Factors

This paper proposes a study related with the downscaling trend in CMOS devices. Some of the structural variants of the MOSFET have been explored and the key performance factors as gate tunneling current, transconductance and output conductance are discussed. The impact of energy quantization on gate tunneling current is studied for double-gate and ultra thin body MOSFETS. Reduced vertical electric field and quantum confinement in the channel of these thin-body devices causes a decrease in gate leakage. Very high transconductance, approaching the ballistic limit, can be achieved provided that technological improvements further increase the electron mobility in the silicon film. The output conductance and Early voltage are severely affected by length scaling as channel length-modulation (CLM) and drain-induced barrier lowering (DIBL) effects become more important, but they are acceptable for channel lengths above 15 nm. . Sanjeev Jain Ssvps Bsd College Of Engg. Vidyanagari Deopur, Dhule Prasad Vinchurkar Ssvps Bsd College Of Engg. Vidyanagari Deopur, Dhule The full text of the article is not available in the cache. Kindly refer the IJCA digital library at www.ijcaonline.org for the complete article. In case, you face problems while downloading the full-text, please send a mail to editor at editor@ijcaonline.org

DC gain analysis of scaled CMOS op amp in Sub-100 nm technology nodes: A research based on channel length modulation effect

Metal-oxide-semiconductor field effect transistor (MOSFET) intrinsic gain degradation caused by channel length modulation (CLM) effect is examined. A simplified model based on Berkeley short-channel insulator-gate field effect transistor model version 4 (BSIM4) current expression for sub-100 nm MOSFET intrinsic gain is deduced, which only needs a few technology parameters. With this transistor intrinsic gain model, complementary metal-oxide-semiconductor (CMOS) operational amplifier (op amp) DC gain could be predicted. A two-stage folded cascode op amp is used as an example in this work. Non-minimum length device is used to improve the op amp DC gain. An improvement of 20 dB is proved when using doubled channel length design. Optimizing transistor bias condition and using advanced technology with thinner gate dielectric thickness and shallower source/drain junction depth can also increase the op amp DC gain. After these, a full op amp DC gain scaling roadmap is proposed, from 130 nm technology node to 32 nm technology node. Five scaled op amps are built and their DC gains in simulation roll down from 69.6 to 41.1 dB. Simulation shows transistors biased at higher source-drain voltage will have more impact on the op amp DC gain scaling over technology. The prediction based on our simplified gain model agrees with SPICE simulation results.

Drain current model for nanoscale double-gate MOSFETs

A closed form inversion charge-based drain current model for a short channel symmetrically driven, lightly doped symmetric double-gate MOSFET (SDGFET) is presented. The model has physical origins, but has some fitting parameters included in order to yield a better match with TCAD device simulations. Velocity saturation and channel length modulation effects are self-consistently included in the model. The incorporation of DIBL effects in the model is based on a solution of the two-dimensional Laplace equation that had been reported earlier and that is believed to be especially suited when the physical gate-oxide thickness is not negligible compared to the silicon body thickness. Addition of support for body doping and low-field mobility degradation is also presented. A very good match is shown in I d–V g , I d–V d and g DS–V d curves and a reasonable match is shown in g m–V g curves, when compared with 2D device simulations. The match in various characteristics is shown for devices as short as 20 nm.

Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design

In this paper, a compact channel thermal noise model for short-channel MOSFETs is presented and applied to the radio frequency integrated circuit (RFIC) design. Based on the analysis of the relationship among different short-channel effects such as velocity saturation effect (VSE), channel-length modulation (CLM), and carrier heating effect (CHE), the compact model for the channel thermal noise was analytically derived as a simple form. In order to simulate MOSFET's noise characteristics in circuit simulators, an appropriate methodology is proposed. The used compact noise model is verified by comparing simulated results to the measured data at device and circuit level by using 65nm and 130nm CMOS technologies, respectively.

Analytical modeling of thermal noise in deep submicron MOSFETs

An analytical modeling of MOSFETs channel noise is proposed by considering short-channel effects of deep submicron MOSFETs, such as mobility degradation, hot carrier, bulk charge, and channel length modulation effect. The model is only dependent on bias, size, and technology of MOSFETs, and hence is suitable for low-noise RF IC design. Noise parameters of MOSFETs are achieved and good agreement between calculated and measured results is demonstrated.

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high- κ dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect.

Influence of Fin Width on the Intrinsic Voltage Gain of Standard and Strained Triple-Gate nFinFETs

This work studies the influence of the fin width on the intrinsic voltage gain of standard and strained Si (sSOI) n-type triple-gate FinFETs with high-k dielectrics and metal gate. It is demonstrated that independent of the fin width the application of strain improves the device transconductance. On the other hand, the device output conductance shows a high dependence on the fin width in strained FinFETs with respect to standard ones. The output conductance degrades if narrow fins are used and improves for wide fins. Narrow strained FinFETs show a degradation of the Early voltage compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect.

A comprehensive analytical on-current model for polycrystalline silicon thin film transistors based on effective channel mobility

A comprehensive analytical ON-state drain current model for poly-Si thin film transistors (TFTs) is developed to accurately fit both transfer and output characteristics of either low or high temperature processed poly-Si TFTs in both n- and p-types, with the same unified analytical form. The model is physical explicitly based and mathematically accurate, with no artificial factors introduced. To accomplish this, (1) the most appropriate model precisely describing the gate voltage dependent mobility degradation effect in poly-Si TFTs is determined from three previously employed models; (2) grain boundary barrier controlled carrier conduction model is adequately incorporated; and (3) a mathematically accurate analytical form for drain current is derived based on gradual channel approximation by introducing a new fitting parameter to describe the effective average channel mobility. Channel length modulation effect is introduced in modeling output characteristic. Applicability and accuracy of the model are demonstrated by fitting both n- and p-types poly-Si TFTs fabricated from very different processes.

Input noise modelling of deep submicron MOSFETs

This paper presents a noise model using the channel length modulation (CLM) effect to calculate the total equivalent noise current, referred to the gate (input) of the MOSFET. It is shown here that for short channel MOSFETs the total input noise depends on the electron warming in the channel, the voltage fluctuations due to the gate polysilicon resistance, and the induced thermal noise at the gate. Taking velocity saturation effect and carrier heating effect in the gradual channel region, complete thermal noise modelling of short-channel MOSFETs including the induced gate noise and its correlation coefficients is presented.

A Sub-1-V, 10 ppm/&lt;formula formulatype="inline"&gt; &lt;tex&gt;$^{\circ}$&lt;/tex&gt;&lt;/formula&gt;C, Nanopower Voltage Reference Generator

An extreme low power voltage reference generator operating with a supply voltage ranging from 0.9 to 4 V has been implemented in AMS 0.35-mum CMOS process. The maximum supply current measured at the maximum supply voltage and at 80degC is 70 nA. A temperature coefficient of 10 ppm/degC is achieved as the combined effect of 1) a perfect suppression of the temperature dependence of mobility; 2) the compensation of the channel length modulation effect on the temperature coefficient; and 3) the absence of the body effect. The power supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz is lower than -53 and -42 dB, respectively. The occupied chip area is 0.045 mm2.