Channel Length Modulation Effect Research Articles

The influence of second-order effect on circuit design

The purpose of this paper is to deeply study and understand the influence of second-order effects (channel length modulation effect, bulk effect, subthreshold conductivity short channel effect) on the performance of electronic devices and circuits, and to propose effective methods and techniques to reduce their negative effects. The author will pay attention to the mechanism and characteristics of channel length modulation effect, bulk effect, subthreshold conductivity and short channel effect, and the key factors leading to their changes. Through theoretical analysis, process inversion and simulation, various effective suppression or compensation strategies are explored to improve the performance of electronic devices and circuits and enhance their reliability and stability. Through the in-depth study of the second-order effect, readers can better understand and solve the influence brought by the second-order effect.

Study on the effect of 65 nm NMOS transistor using SILVACO TCAD

This work aims to study the effect of the short gate length of 65 nm NMOS transistor using SILVACO TCAD. A 65 nm NMOS was designed and virtually fabricated and characterized using the ATHENA and ATLAS process and device simulators, respectively. A shorter gate length is expected to experience short channel effects (SCE) such as channel length modulation and drain induced barrier lowering (DIBL). The SCE was observed from the comparison of the long gate length (0.3 µm) and short gate length (65 nm) NMOS transistors’ performances. The result observed from the ID-VD graph showed that the 65 nm NMOS experienced the channel length modulation where the drain current, ID did not saturate as VD increased with an increment of 1.45 at VD = 3.3 V. Several improvements were done to overcome the SCE which are retrograde well implantation and Halo implantation. A 5 × 1014 cm−3 Boron of 200 keV implant energy and a 5 × 1013 cm−3 Boron of 100 keV implant energy were implanted for the retrograde well implant which was shown to reduce the channel length modulation effect. In addition, from the ID-VG graph, the drain current for the 65 nm NMOS was not zero when VG = 0 V, which indicated the DIBL effect. The phosphorus of 2 × 1012 cm−3 and 1 × 1013 cm−3 concentration was implanted for the Halo implantation. The results showed that the inclusion of Halo implantation has reduced the DIBL effect as the ID-VG plot showed that ID = 0 when VD = 0 with the threshold voltage, VTH = 1.87 V respectively. This shows that the inclusion of retrograde well implant and Halo implantation reduces the channel length modulation as well as DIBL effect of the short gate length NMOS.

A new low voltage low power fully differential CMOS class AB current output stage with unique current drive capability

ABSTRACT This paper presents a novel low-voltage low power fully differential class AB current output stage with high linearity and unique current drive capability. The proposed circuit is based on a simple and efficient structure to obtain high linearity by minimising the channel length modulation effect and also avoids cascade structure to act best in low-voltage applications. Giving the complete analyses and equations of the circuit, its properties are verified by Cadence using TSMC 0.18 µm CMOS parameters. In order to study its performance at the presence of non-idealities, Pre-layout and Post-layout both plus Monte–Carlo simulations are also performed. Under±0.9 V supply and 35 µA output bias current, it can deliver the ever high output current of ±350 mA with THD of −49 dB and output impedance of 2.8 MΩ, which leads to a unique high current drive ratio (Ioutmax/Ibias) of 10,000 and low consumed power of 150 µw in pre-layout simulation. In post-layout plus Monte–Carlo simulation, the results will be as ±320 mA output current, −42 dB THD, 2.2 MΩ output impedance, 40 µA DC current of the output branch, 8000 current drive ratio and 160 µw consumed power. These remarkable results prove the proposed novel COS not only as the unique one in the world but Longley ahead of the yet second rank COS by some unbeatable ratios as 11300×,14×,4× and3× in F T , I outmax , (Ioutmax/power), and current drive, respectively, that promise to keep it as the lead one for many years in low-voltage/power ultra-high current applications.

A W-Band Vector Modulator Using Short-Channel Transistor Current Sources and Impedance Compensation Varactors

A W-band vector modulator based on vector summing with a Gilbert-cell is presented, in which two kinds of error-reducing schemes are applied to the summing circuit. One is to use current sources made of short channel transistors to take advantage of the channel length modulation effect. The other is to introduce impedance correction varactors at the input. It controls both gain and phase by using a digital-to-analog converter (DAC) which is designed to make the output impedance of the summing circuit constant regardless of states. The intrinsic gain and phase errors are also analyzed with the help of a simple current model of a MOS transistor, which explains the error-reducing schemes. It was implemented in 28-nm CMOS technology, which consumes only 7.7mA of DC and occupies an area of 0.11mm2 (excluding pads). The RMS gain error of 0.1dB and the RMS phase error of 1.3° were measured with 4-bit gain and 6-bit phase controls at 94 GHz, where the gain dynamic range was around 15 dB.

Experiment study and analytical modeling of fully solution processed organic thin film transistors with conductive polymer top-gate electrode: Performance optimization

In this paper, various fully solution-processed top-gate bottom contacts organic thin-film transistors based on printed silver nanoparticles electrodes were fabricated, electrically characterized, and analytically modeled. The performance of the designed devices thermally and laser sintered nanoparticles electrodes was investigated. The device based on electrode sintered thermally exhibits improved contacts with an on/off ratio of 1.6 × 103 and a saturation mobility of 1.23 × 10−2 cm2V−1s−1. The current–voltage characteristics of OTFTs in terms of the transfer and output characteristics were also modeled and reproduced using an analytical model. Furthermore, various effects were considered in the used model, including the channel length modulation and contact resistance effects as well as field-effect mobility dependence of the gate voltage. The proposed model results for the devices were found to be in a good agreement with the experimental data in terms of the transfer and output characteristics. It was found that the used analytical model correctly describes the electrical characteristics, and it is proved to be accurate enough to explain the charge transport in these types of OTFTs. The development of such model will certainly help in the design of high-performance nanomaterials based OTFTs and their future advancement as well.

A 0.5–1.7 V Efficient and PVT-Invariant Constant Subthreshold gm Reference Circuit in CMOS

This paper presents a low-power constant subthreshold transconductance reference circuit that produces a constant transconductance by subtracting the output currents of two independent transconductance references. By taking the difference between the output currents of the two independent transconductance references, process, voltage and temperature variations are reduced by minimizing the effects of channel length modulation and drain-induced barrier lowering without relying on feedback to regulate the drain voltage. The proposed reference, fabricated in TSMC’s 130 nm process and testing with off-chip temperature-insensitive resistors, can provide a constant transconductance over a temperature range of −30 to 120°C, and a supply voltage range of 0.5 to 1.7 V. The experimental result of the proposed transconductance reference shows an average variation of ±0.8% over temperature for the entire operating voltage range and an average variation of ±1.97% over voltage for the entire operating temperature range. Through the subtraction, the proposed circuit also shows less variation across process corners compared to the conventional constant transconductance reference. The proposed constant transconductance reference exhibits the highest power efficiency (transconductance over power consumption) amongst the reported constant transconductance references. At 0.5 V, the proposed transconductance reference produces a transconductance of 21.46 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{S}$ </tex-math></inline-formula> , while consuming 1.95 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> .

A Charge Pump Current Mismatch Compensation Design for Sub-Sampling PLL

A current mismatch compensation structure for SSPLL charge pump (CP) is proposed and implemented in a low-power 40.5GHz frequency synthesizer. Transistor's channel-length-modulation (CLM) effect induces SSPLL loop gain distortion and decreases VCO control voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ctrl</sub> ) locking range (LR). The proposed compensated CP uses feedback loops to cancel the CLM effect and hence extends V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ctrl</sub> LR from 0.50V to 0.75V under a 1V supply, without degrading SSPLL noise performance. As a result of the more efficient use of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ctrl</sub> range, VCO capacitor bank setup number is reduced from 10 to 7 to cover the same 10% total tuning range. Due to the low-power dividerless structure with sub-sampling lock detector (SSLD) for frequency acquisition, the SSPLL with the proposed compensated CP consumes only 9.5mW power with 192fs RMS jitter.

High-Drain Field Impacting Channel-Length Modulation Effect for Nano-Node N-Channel FinFETs

Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio have been developed after integrating a 14Å nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. Under the lower gate voltage (VGS-VT) and the higher drain/source voltage VDS, the channel-length modulation (CLM) effect coming from the interaction impact of vertical gate field and horizontal drain field was increased and had to be revised well as the channel length L was decreased. Compared to the 28-nm MOSFETs, the interaction effect from the previous at the tested FinFETs on SOI substrate with the short-channel length L is lower than that at the 28-nm device, which means the interaction severity of both fields for nFinFETs is mitigated, but still necessary to be concerned.

1-kW Boost-type PFC Using a Low-Voltage Series Pass Module for Input Current Shaping

A power factor corrector extended from a previously proposed boost-type structure with power semiconductor filter (PSF) is presented. The concept of the PSF is based on using a series pass device (SPD) to profile the input current and regulate the output voltage, and an input capacitor to circulate the ripple current generated by the boost converter. However, the input capacitor is charged up slowly with small input current around the zero crossings, causing high voltage stress on the SPD. Then, a high-voltage device for the SPD is needed. However, high-voltage devices have large channel length modulation effect, high leakage current, large voltage drop, and slow response. To accelerate the capacitor charging and thus reduce the voltage stress, this article proposes to replace the output diode with a controllable switch. The converter is temporarily operated as a buck converter during the zero crossings with the input capacitor charged up swiftly by the output capacitor. The voltage across the SPD can be kept low over the line cycle, resulting in improved input current waveform and reduced power dissipation. A series pass module constructed by multiple parallel-connected low-voltage devices is used to increase current rating. The devices are regulated to operate around the knee point of the output characteristics to reduce power loss. A 1 kW, 85-265 Vac/400 Vdc prototype has been built and evaluated.

The physics-based model of AlGaN/GaN high electron mobility transistor outer fringing capacitances

&lt;sec&gt; With the development of the application of AlGaN/GaN high electron mobility transistors in the radio frequency field, a capacitance model that can accurately describe the &lt;i&gt;C&lt;/i&gt;-&lt;i&gt;V&lt;/i&gt; characteristics of the device has become an important research topic. The gate capacitance of GaN HEMT can be divided into two parts: intrinsic capacitance and fringing capacitance related to two-dimensional electronic gas (2DEG) electrode. The fringing capacitance plays an important part in the switching device. The outer fringing capacitance &lt;i&gt;C&lt;/i&gt;&lt;sub&gt;ofs/d&lt;/sub&gt; dominates the fringing capacitance and is affected by the bias applied, especially the drain outer fringing capacitance &lt;i&gt;C&lt;/i&gt;&lt;sub&gt;ofd&lt;/sub&gt;.&lt;/sec&gt;&lt;sec&gt; In order to establish the &lt;i&gt;C&lt;/i&gt;&lt;sub&gt;ofd&lt;/sub&gt; model which is related to the bias condition, the physics-based model of &lt;i&gt;C&lt;/i&gt;&lt;sub&gt;ofd&lt;/sub&gt; is established based on the conformal mapping, including the drain channel length variable. Since the drain channel length is related to the bias applied, the channel length modulation effect can be used to study how bias apllied effect the channel, and the relationship between &lt;i&gt;C&lt;/i&gt;&lt;sub&gt;ofd&lt;/sub&gt; and the bias condition is obtained. In addition, the threshold voltage variable is introduced when the channel length modulation effect is considered, and the threshold voltage drift caused by changes in the internal parameters and temperature of the device is studied using the threshold voltage variable in the model, and the relationship between &lt;i&gt;C&lt;/i&gt;&lt;sub&gt;ofd&lt;/sub&gt; and threshold voltage and temperature under different bias was obtained.&lt;/sec&gt;&lt;sec&gt; It is found from the results of the study that as drain bias increases from zero, the channel length modulation effect keeps &lt;i&gt;C&lt;/i&gt;&lt;sub&gt;ofd&lt;/sub&gt; unchanged at lower drain bias. When the drain bias continues to increase, &lt;i&gt;C&lt;/i&gt;&lt;sub&gt;ofd&lt;/sub&gt; begins to decay again, and its decay rate slows down with the increase of gate bias. The decrease of donor impurity concentration and Al component in AlGaN barrier layer may increase the threshold voltage, which will strengthen the channel length modulation effect on &lt;i&gt;C&lt;/i&gt;&lt;sub&gt;ofd&lt;/sub&gt;, resulting in linear attenuation of &lt;i&gt;C&lt;/i&gt;&lt;sub&gt;ofd&lt;/sub&gt;. With the increasing of drain bias, the influence of threshold voltage shift on &lt;i&gt;C&lt;/i&gt;&lt;sub&gt;ofd&lt;/sub&gt; is enhanced, and the change of device operating temperature will enhance the threshold voltage shift and cause the deviation of &lt;i&gt;C&lt;/i&gt;&lt;sub&gt;ofd&lt;/sub&gt;. Moreover, with the continuous increase of drain bias, &lt;i&gt;C&lt;/i&gt;&lt;sub&gt;ofd&lt;/sub&gt; becomes more sensitive to the temperature variation.&lt;/sec&gt;

A Low Power and Low Current-Mismatch Charge Pump with Dynamic Current Compensation

A novel low power charge pump (CP) that minimizes the mismatch between the charging and the discharging currents is proposed in this paper. The switching circuit with dynamic current compensation is used to reduce the power consumption of the proposed CP. In addition, precise current replication which makes use of the resistors and the low offset operational amplifiers (OTA) can enable a reduction in current mismatch caused by process mismatch. Meanwhile, the high output impedance can reduce the current mismatch caused by the channel length modulation effect. Based on the 0.18[Formula: see text][Formula: see text]m deep-Nwell CMOS process, the proposed CP can reduce the overall power consumption by 56% compared with the CP without current compensation, reduce the current mismatch caused by process mismatch to less than 0.9% and reduce the current mismatch caused by the channel length modulation effect to less than 0.01% over the output voltage ranging from 0.3 to 1.5[Formula: see text]V with 1.8[Formula: see text]V supply.

Analysis of DIBL Effect and Negative Resistance Performance for NCFET Based on a Compact SPICE Model

In this paper, we describe an improved SPICE model for the negative capacitance field-effect transistor (NCFET). According to the law of conservation of charge, the model is built based on the relationship between the gate charge of the MOSFET and the charge reserved by the ferroelectric layer and includes the parasitic resistance and capacitance into consideration. Based on the model, the drain-induced barrier lowering (DIBL) and the negative resistance (NR) of the NCFET are analyzed. Finally, taking two well-known analog blocks (the current mirror and the latch comparator) for example, impacts of the DIBL effect and the NR property on analog circuit performances are discussed. Thanks to utilization of the NR feature, not only can impacts of the DIBL effect and the channel-length modulation (CLM) effect be alleviated to improve the mirroring accuracy, but also the comparison speed of the latch comparator be accelerated.

Improvement of gm/ID Method for Detection of Self-Heating Effects

This paper presents an improvement on the use of the transistor efficiency to verify the presence of self-heating effects using only DC measurements. Applying this improved method on FinFET devices allowed the establishment of a comparison of the self-heating effect among devices with different channel lengths, despite their different channel length modulation effects.

Analytical high frequency GaN HEMT model for noise simulations

A compact high frequency model for AlGaN/GaN HEMT device valid for noise simulations is presented in this paper. The model is developed based on active transmission line approach and linear two port noise theory that makes it applicable for quasi static as well as non-quasi static device operation. The effects of channel length modulation and velocity saturation are discussed. Moreover, the effect of the gate leakage current on the noise performance of the device is investigated. It is shown that there is an apparent increase in noise generated in the device due to the gate current related shot noise. The common noise figures of merit for HFET are calculated and verified with experimental data.

A low-voltage, low-power voltage reference based on subthreshold MOSFETs

A novel low-voltage low-power CMOS voltage reference independent of temperature is presented in this design. After considering the combined effect of (1) a perfect suppression of the temperature dependence of mobility; (2) the compensation of the channel length modulation effect on the temperature coefficient, a temperature coefficient of 10 ppm/[Formula: see text]C is achieved. Moreover, by adopting the subthreshold MOSFETs, there are no resistors used in the proposed structure. Therefore, the maximum supply current measured at the maximum supply voltage is 70 nA and at 80[Formula: see text]C. The circuit can be used as a voltage reference for high performance and low power dissipation on a single chip.

Thermal stress probing the channel-length modulation effect of nano n-type FinFETs

The 3D FinFETs deed provide the impressive gate controllability, especially in drive speed of transistors. However, this advantage relatively brings some drawbacks in channel length modulation (CLM) causing the difficulty in device model establishment. In this work, besides the study of n-type FinFETs in CLM effect, the previous study in 2D HK/MG nMOSFETs at room temperature is also referred and discussed with 3D FinFETs. The influence to the CLM effect at low gate bias is more apparent, speculating the quality of surface channel contributing the depletion width near drain site. The depletion width is usually influenced by raised temperature. And the CLM effect is gradually moved from the low-field dominated to the mid-field as the temperature increased at short-channel device no matter what the VT implant energy is, but not suitable to the others.

Charge-Based Compact Model for DC Current in Organic TFT Including Non-Linear Injection Effects with a Close Link to Electrical Device Parameter

In this paper a closed-form current model for organic TFTs is presented which leads to a charge-based continuous current model with threshold voltage and slope as model parameters, while still keeping a single expression valid from below to above threshold operation. Most compact models for organic field-effect transistors (OFETs) are based on a two-piece description: a set of equations for above threshold operation is combined with a current model valid in subthreshold region by means of an analytical smoothing function [1]. Thereby the threshold voltage is introduced as fitting parameter without any relation to physical parameters. In [2] a charge-based current model with a continuous equation valid in all regions of operation has been presented. While solving Poisson’s equation the model preserves a close link to physical parameters like shallow and deep trap densities and avoids the introduction of a threshold voltage and subthreshold slope as model parameters. However, from a circuit designer’s perspective a model providing a close link to electrical device parameters is desirable because parameters as threshold voltage and slope can easily be extracted from I/V curves and are performance measures of a device. In this paper an improvement of the model from [2] is presented which leads to a charge-based C∞-continuous current model with threshold voltage and slope as model parameters, while still keeping a single expression valid from below to above threshold operation. To include the effect of hopping transport the empirical power-law mobility model [3] and a contact resistance [4] have been incorporated in the effective mobility. Channel length modulation effects have been included according to [5]. Furthermore, from physical parameters given by trap densities the threshold voltage and subthreshold slope of the device can be calculated. In the case of co-planar device structures the output characteristics in the linear operation regime show a superlinear behaviour due to non-linear injection effects. If the barrier height between source electrode and the channel material is not negligible the channel current is limited by the source injection current. The Schottky barrier height is modulated by the gate and drain potential. A strong electric field causes thinning of the barrier, allowing more carriers to enter channel. An analytical equation for the electric field at the injection barrier has been derived by applying the conformal mapping technique. The bias-dependent lowering of the Schottky barrier, and hence the maximum injection current can be calculated. An equivalent resistance of the Schottky barrier is calculated from the voltage drop Vds and the maximum possible injection current. To arrive at a closed-form current equation for the intrinsic device together with the injecting Schottky barrier this equivalent resistance is incorporated in the current equation by a first order approximation which is commonly used for the consideration of parasitic resistances. In this case the equivalent resistance is bias dependent and reduced with increasing Vds due to Schottky barrier lowering. The model has been validated vs. measurements on devices with small molecule organic semiconductors (Fig. 1, 2). The results show good agreement, even for the 1st and 2nd derivatives of the transfer characteristics. Acknowledgements: This project was funded by the German Federal Ministry of Education and Research contract No.03FH013PX2 (FhProfUnt). This project was also funded by the Horizon 2020 Programme of the European Union under contract RISE 2014 645760 ("DOMINO"). We acknowledge CEA-Liten (Grenoble) and Max Planck Institute for Solid State Research (Stuttgart) for providing measurement data. We thank AdMOS GmbH for support and Keysight Technologies for license donation of IC-CAP.

Charge based, continuous compact model for the channel current in organic thin-film transistors for all regions of operation

In general most modeling approaches for organic field-effect transistors (OFETs) are based on the typical MOSFET equations. The threshold voltage is usually a fitting parameter without relation to physical parameters hence the impact of their variability on the threshold voltage is not clear. The presented modeling approach is charge based with a continuous equation for the channel current in organic field-effect transistors from below to above threshold. The model provides a physics based parameter set related to trap states, and a compatible parameter set from a circuit designer’s perspective. An expression for the threshold voltage is derived depending on the density of trap states. The model considers a power-law mobility model, parasitic contact resistances and channel length modulation effects and is verified with measurements on OFETs fabricated with small molecules.

A Lateral Regulator Diode with Field Plates for Light-Emitting-Diode Lighting**Supported by the National Natural Science Foundation of China under Grant No 61376080.

A lateral current regulator diode (CRD) with field plates is proposed and experimentally demonstrated. The proposed CRD is based on the junction field-effect transistor (JFET) structure. A cathode field plate is adopted to alleviate the channel-length modulation effect and to improve the saturated I—V characteristics. An anode field plate is induced to achieve a high breakdown voltage VB of the CRD. The influence of the key device parameters on the I—V characteristics of the lateral CRD are discussed. Experimental results show that the proposed CRD presents good I—V characteristics with a high VB about 180 V and a low knee voltage (Vk) below 3 V. Furthermore, the proposed CRD has a negative temperature coefficient. The well characteristic of the proposed CRD makes it a cost-effective solution for light-emitting-diode lighting.

A LTPS-TFT pixel circuit for active matrix organic light emitting diode based on improved current mirror

In this paper, a voltage-driving and current compensation method for active matrix organic light emitting diode (AMOLED) displays is proposed. An improved current mirror is introduced into the pixel circuit to overcome the channel length modulation effect of TFTs. The SPICE simulation results show that the proposed pixel circuit not only effectively compensates for non-idealities related with deviations of μ and VT in TFTs, the OLED degradation, but also offers a less setting time and guarantees a good liner relationship between VDATA and IOLED.