Abstract
A current mismatch compensation structure for SSPLL charge pump (CP) is proposed and implemented in a low-power 40.5GHz frequency synthesizer. Transistor's channel-length-modulation (CLM) effect induces SSPLL loop gain distortion and decreases VCO control voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ctrl</sub> ) locking range (LR). The proposed compensated CP uses feedback loops to cancel the CLM effect and hence extends V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ctrl</sub> LR from 0.50V to 0.75V under a 1V supply, without degrading SSPLL noise performance. As a result of the more efficient use of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ctrl</sub> range, VCO capacitor bank setup number is reduced from 10 to 7 to cover the same 10% total tuning range. Due to the low-power dividerless structure with sub-sampling lock detector (SSLD) for frequency acquisition, the SSPLL with the proposed compensated CP consumes only 9.5mW power with 192fs RMS jitter.
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