High-Drain Field Impacting Channel-Length Modulation Effect for Nano-Node N-Channel FinFETs

Mu-Chun Wang,Wen-How Lan,Wen-Ching Hsieh,Chii-Ruey Lin,Wen-Shiang Liao,Wei-Lun Chu

doi:10.3390/cryst11030262

Abstract

Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio have been developed after integrating a 14Å nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. Under the lower gate voltage (VGS-VT) and the higher drain/source voltage VDS, the channel-length modulation (CLM) effect coming from the interaction impact of vertical gate field and horizontal drain field was increased and had to be revised well as the channel length L was decreased. Compared to the 28-nm MOSFETs, the interaction effect from the previous at the tested FinFETs on SOI substrate with the short-channel length L is lower than that at the 28-nm device, which means the interaction severity of both fields for nFinFETs is mitigated, but still necessary to be concerned.

Highlights

With the evolution of process technology and the need of marketing, exploring the high speed, low cost, and high-volume capacity in integrated-circuit (IC) chips is the development trend in the modern semiconductor industry [1,2,3]
In order to obtain ultra-high density metal-oxide-semiconductor FET-like (MOSFET) IC products, a 3D fin field-effect transistor (FinFET) device has been incorporated as a promising candidate as compared to other double gate device structures [8,9] owing to its process compatibility with conventional logic devices
Considering the 3-D FinFET device upon SOI wafer with an ultra-thin Si-fin, it is feasible to be employed to deep sub-nano process technology such as the sub14-nm node [52,53,54]

Summary

Introduction

With the evolution of process technology and the need of marketing, exploring the high speed, low cost, and high-volume capacity in integrated-circuit (IC) chips is the development trend in the modern semiconductor industry [1,2,3]. As the process of technology enters the nano-node generation, seeking the better device structure compatible with the Si-based process flow is a good way to promote the drive current and product competition. The fin field-effect transistor (FinFET) structure is one of the impressive candidates in the tremendous competitive FET devices [4,5,6,7]. In order to obtain ultra-high density metal-oxide-semiconductor FET-like (MOSFET) IC products, a 3D FinFET device has been incorporated as a promising candidate as compared to other double gate device structures [8,9] owing to its process compatibility with conventional logic devices.

Brief Illustration of Device Formation

Results and Discussion

Conclusions