Channel Hot Electron Research Articles

Explanation of P/E Cycling Impact on Drain Disturb in Flash EEPROMs Under CHE and CHISEL Programming Operation

The impact of program/erase (P/E) cycling on drain disturb in NOR Flash EEPROM cells under channel hot electron (CHE) and channel-initiated secondary electron (CHISEL) programming operation is studied. Charge gain disturb increases and charge loss disturb decreases after cycling under CHE and CHISEL operation. Carefully designed experiments and fullband Monte Carlo simulations were used to explain this behavior. P/E cycling induced degradation in gate coupling coefficient and the resulting increase in source/drain leakage, reduction in band-to-band tunneling and change in carrier injection area seems to explain well the behavior of CHE and CHISEL drain disturb after cycling.

Distribution and Impact of Local Trapped Charges in Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) Memory

In this paper we propose a two-transistor model with an RPT for the punch-through resistor in the silicon-oxide-nitride-oxide-silicon (SONOS) memory cell. With this model, the subthreshold leakage current induced by the local trapped charges in silicon nitride and the impact on the cell's read characteristics are studied. Some solutions to decrease this leakage current and change the distribution of the trapped charges are proposed and analyzed, including programming condition optimization, the channel initiated secondary electron (CHISEL) programming, and cell structure optimization. Moreover, using the CHISEL or channel hot electron (CHE) programming, the influences on the programming and the erase characteristics of different charge distributions are investigated.

Embedded Ultra High Density Flash Memory Cell and Corresponding Array Architecture

A novel flash memory cell fabricated by standard complementary metal oxide semiconductor (CMOS) logic process and its corresponding array architecture is presented. The cell which consists of two metal-oxide-semiconductor field effect transistors (MOSFET) in series is programmed by channel current induced drain avalanche hot hole and erased by channel hot electron injection. With novel operation principles and array architecture, a feature-sized n-MOSFET per non-volatile memory bit is successfully demonstrated and the CMOS-process-based flash cell size can be as small as multi-gated flash memory. The smallest bit area of a CMOS-process-based flash memory cell with good programming and erasing characteristics along with endurance up to 105 cycles, 10 years excellent read disturbance and data retention characteristics of data retention at 150°C is proposed. With its small cell size and full compatibility with standard CMOS logic process, the novel flash memory cell can be easily adapted in highly integrated very large scale integration (VLSI) systems.

An Analytical Programming Model for the Drain-Coupling Source-Side Injection Split Gate Flash EEPROM

This paper presents a compact and accurate analytical model for evaluating the programming behaviors of the drain-coupling source-side injection (SSI) split-gate Flash memory. Starting with the bias-dependent and time-varying drain coupling ratio, a programming model is developed on the basis of the constant barrier height approximation and Lucky-electron model to express the full transient injection current, peak lateral electric field, and storage charge as functions of technological, physical, and electrical parameters. The extracted re-direction mean-free path of the SSI device is smaller than that of the channel hot-electron counterpart by one order of magnitude, which provides the physical intuition for the derived high injection efficiency of around 2/1000. The intrinsic coupling ratio depends only on technological parameters and is presented as the design index of the device. The usefulness of this model is its ability of constructing the complete operation plot of the time-to-program versus the programming voltage for various reliability windows and tunable technological parameters. Besides, the variance of the read current distribution of a memory array is also analytically predicted.

High-Density Single-Poly Electrically Erasable Programmable Logic Device for Embedded Nonvolatile Memory Applications

A novel electrically erasable programmable logic device (EEPLD) memory cell with new program and erase operations fabricated by a standard complementary metal–oxide–semiconductor (CMOS) logic process is presented. The cell which consists of two metal–oxide–semiconductor field effect transistor (MOSFET) transistors in series is programmed by select-gate-controlled drain avalanche hot hole injection and erased by channel hot electron injection. The cell exhibits good programming and erasing characteristics along with endurance up to 105 cycles, and 1000 h of data retention at 150°C. A new self-converged programming scheme is investigated for multilevel or analog storage. Without a P-well or an N-well serving as a coupling gate, the novel cell provides the smallest area size per bit reported for a single-poly nonvolatile memory. With its small cell size and full compatibility with the standard CMOS logic process, the novel EEPLD can be easily adopted in highly integrated VLSI systems.

Evidence for a Composite Interface State Generation Mode in the CHE-Stressed Deep-Submicrometer n-MOSFET

Results from channel hot-electron stressing of 0.18-/spl mu/m n-MOSFETs indicate that, for typical drain stress voltages ranging from 2-3 V, a significant fraction of the Si-SiO/sub 2/ interface states is in fact generated by the majority of the less energetic (/spl les/qV/sub d/<3 eV) electrons in the channel, as opposed to the usual perception that injection of the more energetic (>3 eV) high-energy tail (HET) electrons plays a dominant role. The role of the minority HET electrons, however, becomes increasingly dominant as the drain voltage is reduced. On the basis that the HET electrons gain excess energy through secondary means, this composite interface state generation mode may have a significant impact on the accuracy of hot-carrier reliability projection.

Erratic Cell Behavior in Channel Hot Electron Programming of NOR Flash Memories

This paper describes for the first time an erratic behavior found in NOR array cells of flash memories after cycling when programming is performed by channel hot electron injection. The effects of different program conditions (i.e., drain and bulk bias, as well as program speed) on such an erratic behavior are discussed and a possible explanation is given. Implications in terms of memory reliability are discussed, in particular for multilevel applications.

Cycling Endurance of NOR Flash EEPROM Cells Under CHISEL Programming Operation—Impact of Technological Parameters and Scaling

The impact of technological parameter (channel doping, source/drain junction depth) variation and channel length scaling on the reliability of NOR flash EEPROM cells under channel initiated secondary electron (CHISEL) programming is studied. The best technology for CHISEL operation has been identified by using a number of performance metrics (cycling endurance of program/erase time, program/disturb margin) and scaling studies were done on this technology. It is explicitly shown that from a reliability perspective, bitcell optimization for CHISEL operation is quite different from that for channel hot electron (CHE) operation. Properly optimized bitcells show reliable CHISEL programming for floating gate length down to 0.2 /spl mu/m.

Compact Modeling of a Flash Memory Cell Including Substrate-Bias-Dependent Hot-Electron Gate Current

We propose a compact model for a Flash memory cell that is suitable for circuit simulation. The model includes a hot-electron gate current model that considers not only channel hot electron injection but also channel initiated secondary electron injection to express properly substrate bias dependence of gate current. Tunneling gate current for erasing is expressed by the BSIM4 tunneling gate current model. Good agreement between measured and simulated results of both programming and erasing characteristics for 130-nm technology Flash memory cells indicates that our model is useful in designing and optimizing circuit for Flash memories.

Performance, Degradation Monitors, and Reliability of the CHISEL Injection Regime

This work reviews recent results concerning the performance and reliability of the channel initiated secondary electron (CHISEL) injection regime, often used to boost the programming speed of Flash memories. In order to relate the CHISEL behavior to the physical conditions existing in the device, the injection efficiency of CHISEL is studied on single transistors. A comparison between the degradation in the CHISEL injection and in the channel hot electron (CHE) stress regime has been also performed, and the most relevant electrical monitor for the degradation is assessed. It is confirmed that the CHISEL mechanism is promising for the realization of faster and more efficient Flash memory cells.

A Drain Avalanche Hot Carrier Lifetime Model for n- and p-Channel MOSFETs

A simple and physical drain avalanche hot carrier lifetime model has been proposed. The model is based on a mechanism of interface trap generation caused by recombination of hot electrons and hot holes. The lifetime is modeled as /spl tau/(I/sub d//W)/sup 2//spl prop/(I/sub sub//I/sub d/)/sup -m/. The formula is different from the conventional /spl tau/I/sub d//W-I/sub sub//I/sub d/ model in that the exponent of I/sub d//W is 2, which results from the assumed mechanism of the two-carrier recombination. It is shown that the mechanism gives a physical basis of the empirical /spl tau/-I/sub sub//W model for NMOSFETs. The proposed model has been validated experimentally both for NMOSFETs and for PMOSFETs. Model parameters extracted from experimental data show that carrier critical energies for creating damage are lower than the interface potential barriers. It is supposed that oxide band edge tailing enables low-energy carriers to create the damage. The channel hot electron condition becomes the worst case in short channel NMOSFETs, because gate voltage dependence of the maximum channel electric field decreases.

Inverted sidewall spacer and inner offset oxide process for excellent 2-bit silicon-oxide-nitride-oxide-silicon memory under 100nm gate length

By forming physically separated 30nm twin ONOs with an inverted sidewall spacer patterning method under a single gate based on damascene gate process, problems of the charge distribution and diffusion during and after the channel hot electron injection program in the 2-bit operation of the localized trap memory were cleared out. The two charge storage nodes of nitride with length of 30nm under the 100nm channel length can be created by adopting inverted amorphous polysilicon spacer and inner offset oxide process made in the groove. This inverted amorphous silicon spacer process does not suffer from unit-cell size increase, photoresolution limit, nor photo misalign between gate and oxide-nitrogen-oxide structures. In addition, the inner offset oxide protects the ultrathin amorphous Si spacer from the loss due to the subsequent etch process and plays an important role of minimizing the overlap between gate and source/drain. In this structure, the spatial distribution can be controlled and lateral charge diffusion is blocked, so that stable 2-bit operation with high erase speed and reliabilities such as endurance and retention can be achieved, compared with the conventional single silicon-oxide-nitride-oxide-silicon structure under 100 nm regimes.

Write/Erase Cycling Endurance of Memory Cells With SiO&amp;lt;tex&amp;gt;$_2$&amp;lt;/tex&amp;gt;/HfO&amp;lt;tex&amp;gt;$_2$&amp;lt;/tex&amp;gt;Tunnel Dielectric

The write/erase cycling endurance of low voltage floating-gate memory cells programmed and erased by tunneling through a SiO/sub 2//HfO/sub 2/ dual layer tunnel dielectric stack is investigated. The use of fixed single pulse program and erase conditions leads to fast shifting (after /spl sim/1000 cycles) of the threshold voltage window, so that only a limited number of write/erase cycles can be achieved. Increasing the write and erase duration quickly leads to an excessive erase time so that a different erase method has to be used. Improvement of the erase behavior and cycling endurance has been obtained by a combination of two methods. Inclusion of soft write pulses between the erase pulses reduces the amount of charge trapped in the tunnel dielectric and therefore limits the increase in erase time. Also, the erase voltage can progressively be raised in order to further limit the erase time, leading to an endurance of 10 000 cycles on the considered cells. When combining the SiO/sub 2//HfO/sub 2/ stack with channel hot electron injection so that tunneling is only required in one direction, 100 000 write/erase cycles are demonstrated with minimal change of the memory window.

Quasisuperlattice storage: A concept of multilevel charge storage

A concept of the quasisuperlattice storage has been demonstrated in this study. Under suitably operated voltage, two apparent states of charge storage can be distinguished. The memory effects are due to the multilevel storage in the quasisuperlattice. Also, the a-Si quantum wells provide a feasible design for the 2 bit per cell nonvolatile memory devices. The operation of the 2 bit per cell needs to be performed by Fowler–Nordheim tunneling instead of conventional channel hot electron injection. Additionally, the dual read operation of the source and drain sides for conventional SONOS 2bit∕cell device is not necessary, which simplifies the circuit design engineering.

Temperature Effect on Read Current in a Two-Bit Nitride-Based Trapping Storage Flash EEPROM Cell

The temperature effect on the read current of a two-bit nitride-storage Flash memory cell is investigated. In contrast to a conventional silicon-oxide-nitride-oxide (SONOS) cell with uniform Fowler-Nordheim (FN) programming, a significant high-V/sub T/ state read current increase, which results in the read window narrowing at high temperature, is observed in a channel hot electron (CHE) programmed cell. The increment of high-V/sub T/ state leakage current shows a positive correlation with program/erase threshold voltage window. Since the temperature effect is very sensitive to a locally trapped charge profile, a two-dimensional simulation with a step charge profile is employed to characterize the relationship between current increment and both charge width and charge density.

A novel SONOS nonvolatile flash memory device using substrate hot-hole injection for write and gate tunneling for erase

In this work, we describe a novel SONOS device suitable for future nonvolatile flash memories. Substrate hot-hole injection (HHI) through a bottom oxide is used for write and gate tunneling through a thin top oxide is employed for erase. We present device DC and dynamic characteristics at low voltages (<10 V) for SONOS devices with a gate dielectric stack consisting of a 3.8 nm bottom oxide, 1.5 nm nitride and 3.0 nm top oxide. We obtain a reduction in power consumption by 4 orders of magnitude, an improvement in retention by 90%, and an improvement in subthreshold swing by 40% with a novel write/erase technique compared with Substrate HHI for erase and channel hot electron (CHE) injection for write.

Scalable 2-bit silicon–oxide–nitride–oxide–silicon (SONOS) memory with physically separated local nitrides under a merged gate

A physically separated 2-bit SONOS memory with a single gate is fabricated for the first time. By forming physically separated 30-nm twin ONOs with an inverted sidewall spacer patterning method and damascene process under a merged-triple gate, the decrease of charge distribution and diffusion during and after CHEI (channel hot electron injection) program in 2-bit operation of the localized trap memory is observed in devices with the gate length of 90 nm. The inverted amorphous silicon spacer and the damascene gate process does not suffer from unit-cell size increase, lithographic resolution limit, and miss-alignment between gate and ONOs. Comparing with a conventional single SONOS memory (SSM), this novel twin SONOS memory (TSM) cell can maintain the better control of trapped charge distribution due to the strong diffusion barrier of charges. As a result, better 2-bit operation, endurance and retention than SSM, and absence of disturbance can be obtained in the short (sub 90 nm) gate length devices.

Characterizing damage to ONO dielectrics induced during programming SONOS/NROM TM non-volatile semiconductor memory (NVSM) devices

We present experimental results on scaled silicon-oxide–nitride-oxide–silicon (SONOS/NROM TM) transistors using a variety of programming mechanisms. These devices store holes and electrons in traps in a nitride layer in the gate dielectric. Programming is achieved with a variety of mechanisms: modified Fowler–Nordheim (MFN) tunneling, channel hot electron injection (HEI), and hot hole injection (HHI). All measurements are performed on transistors with gate dielectrics composed of a tunneling oxide ( X OT), silicon-nitride charge-storage layer ( X N), and a blocking oxide ( X OB) of 4, 4.2, and 4.4 nm (NROM TM) or 2, 7, and 4 nm (SONOS), respectively. Charge pumping measurements are employed to characterize the interface trap density of fresh devices and monitor the generation of new interface traps during write/erase operations. We study the damage to ONO dielectrics caused by write/erase cycling by comparing interface trap densities for SONOS/NROM TM devices programmed using varying charge-injection mechanisms after 10 6 write/erase cycles for 10 year retention.

Nonlocal Hot-Electron Injection as the Mechanism for the Predominant Source-Side Gate Oxide Degradation in CHE-Stressed Deep Submicrometer n-MOSFETs

A possible mechanism behind the predominant source-side gate oxide degradation in channel hot-electron (CHE)-stressed deep submicrometer n-MOSFETs is presented. The role of a nonlocal hot-electron injection mechanism, arising possibly from carrier-to-carrier interaction and/or impact ionization feedback, is emphasized. The latter effect is prominently revealed through a systematic stress scheme that employs a reverse substrate bias. Oxide degradation behaviour is shown to be consistent with the anode electron-energy model. The more severe source-side oxide degradation may be attributed to nonlocally injected tertiary electrons possessing greater available energy on arrival at the anode (gate), as a result of a coupled heating process.

Drain disturb during CHISEL programming of NOR flash EEPROMs-physical mechanisms and impact of technological parameters

The origin of drain disturb in NOR Flash EEPROM cells under channel initiated secondary electron (CHISEL) programming operation is identified. A comparative study of drain disturb under channel hot electron (CHE) and CHISEL operation is performed as a function of drain bias and temperature on bitcells having different floating gate length and junction depth. The disturb mechanism is shown to originate from band-to-band tunneling under CHISEL operation, unlike that under CHE operation that originates from source-drain leakage. The effect of technological parameters (channel doping and drain junction depth) on CHISEL drain disturb is studied for both the charge gain (erased cell) and charge loss (programmed cell) disturb modes. Fullband Monte Carlo device simulations are used to explain the experimental results. It is shown that methods for improving CHISEL programming performance (higher channel doping and/or lower drain junction depth or halo) increase drain disturb, which has to be carefully considered for efficient design of scaled cells.