Channel Hot Electron Research Articles

Design of Wireless Multiple Gases Complementary Architecture Sensors Based on SnSe2 and PtSe2 Layered Films and Oscillating Circuits

AbstractOwing to the increasing demand for monitoring harmful toxic gases using small‐sized low‐power‐consumption gas sensors, a room‐temperature wireless complimentary gas sensor incorporating layered materials is proposed and demonstrated. The compact design allows the sensing module to be installed under all conditions and facilitates multiple detections of toxic gas. Highly chemical‐resistance‐sensitive materials based on n‐type SnSe2 and p‐type PtSe2 layered materials prepared by the plasma‐assisted chemical vapor reaction (PACVR) method at low temperatures are integrated with an oscillation circuit and antenna fabricated by a 28‐nm CMOS high‐k metal gate logic process to achieve dense, low‐powered, and wireless characteristics. By pairing n‐ and p‐type layered semiconductors, the gas sensors feature less influence from the surroundings, such as temperature and humidity, and enhance sensitivity to the target gas simultaneously. The wireless sensing detection method enables a sensor to make signal reception more convenient. Furthermore, a wireless gas sensor with self‐converging calibration using the advantage of a floating‐gate (FG) transistor to control the charge quantity by shifting the threshold voltage (Vth) of each transistor via the channel hot electron injection effect, which helps to reduce the impact of process variations, minimizing readout errors, is proposed.

Optimized operation scheme of flash-memory-based neural network online training with ultra-high endurance

With the rapid development of machine learning, the demand for high-efficient computing becomes more and more urgent. To break the bottleneck of the traditional Von Neumann architecture, computing-in-memory (CIM) has attracted increasing attention in recent years. In this work, to provide a feasible CIM solution for the large-scale neural networks (NN) requiring continuous weight updating in online training, a flash-based computing-in-memory with high endurance (109 cycles) and ultra-fast programming speed is investigated. On the one hand, the proposed programming scheme of channel hot electron injection (CHEI) and hot hole injection (HHI) demonstrate high linearity, symmetric potentiation, and a depression process, which help to improve the training speed and accuracy. On the other hand, the low-damage programming scheme and memory window (MW) optimizations can suppress cell degradation effectively with improved computing accuracy. Even after 109 cycles, the leakage current (I off) of cells remains sub-10pA, ensuring the large-scale computing ability of memory. Further characterizations are done on read disturb to demonstrate its robust reliabilities. By processing CIFAR-10 tasks, it is evident that ~90% accuracy can be achieved after 109 cycles in both ResNet50 and VGG16 NN. Our results suggest that flash-based CIM has great potential to overcome the limitations of traditional Von Neumann architectures and enable high-performance NN online training, which pave the way for further development of artificial intelligence (AI) accelerators.

Characterization of trap evolution in GaN-based HEMTs under pulsed stress

In this paper, the evolution of traps in GaN-based high-electron-mobility transistors under pulsed thermal stress and the combined effect of thermal stress and electrical stress are studied. By applying impulse stresses of different powers to the device, collecting transient current response curves, and accurately extracting the time constant and absolute peak changes of the traps by employing the Bayesian inverse convolution theory time constant spectral technique, we analyzed the evolution of the traps under the action of impulse stress and clarified the influence and degradation mechanism of the thermal stress, as well as the combined action of thermal stress and electrical stress, on the evolution of traps. The results show that under pulsed stress, the decrease in electron mobility with increasing temperature leads to a decrease in device drain current, and the degradation of the device is exacerbated owing to channel hot-electron injection.

Anneal Behavior of Total Ionizing Dose Irradiated UTBB FD-SOI n-MOSFETs Activated by Hot Carrier Stress

In this article, anneal behavior of total ionizing dose (TID) irradiated ultrathin body and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) n-MOSFETs activated by hot carrier stress is observed and discussed. Hot carrier experiments applied on TID irradiated and unirradiated devices show that TID-induced positive oxide charges in buried oxide (BOX) can be neutralized by channel hot electrons, while no additional charged traps are generated. By considering the interactions of charged oxygen vacancies and channel hot electrons, the tunneling anneal process assisted by multiphonon emission is proposed.

Extraction of Dynamic Threshold Voltage in Resistive Load Hard Switching Operation of Schottky-Type p-GaN Gate HEMT

Threshold voltage (VTh) drift of Schottky-type p-GaN gate high-electron mobility transistor (HEMT) was analyzed under high-voltage and hard switching conditions with a resistive load (R-Load). To overcome the distortion in the drain current (ID) – gate voltage (VG) curve caused by the internal drain capacitance (IDisp) charging current during the switching transients, a method is presented to accurately measure dynamic VTh through appropriate correction of IDisp. The dynamic variation of VTh was tracked with a gate-drive rise/fall times of 200 ns. During the switching operation, VTh increases rapidly at the beginning and then saturates at a stable value. This is attributed to the gate forward current during turn-on that increases the hole depletion of the p-GaN gate through the AlGaN barrier. The dynamic VTh increases linearly at a rate of 40% with the increase of gate turn-on voltage. VTh is independent of duty cycle but minorly increases with frequency at high voltages, suggesting that channel hot electrons be injected into the AlGaN barrier and p-GaN.

Modeling of Classical Channel Hot Electron Degradation in n-MOSFETs Using TCAD

A technology CAD (TCAD) setup is used to calculate the channel hot electron (CHE) induced parametric drift in n-MOSFETs. The setup uses reaction-diffusion-drift model and utilizes carrier energy, vertical electric field, and lattice temperature effects, to calculate the time kinetics of trap generation and its impact on the device parametric drift. Experimental data from published reports, measured using different probes, for midgate bias stress under varying drain bias ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 3$ </tex-math></inline-formula> –8 V) and temperature (0 °C–100 °C) are modeled, in classical devices having different channel lengths (2.0– <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.3~\mu \text{m}$ </tex-math></inline-formula> ) and oxide thicknesses (35–5 nm). The impact of device dimension scaling on the spatial distribution of generated traps and their impact on the device parametric drift are discussed.

On the Channel Hot-Electron’s Interaction With C-Doped GaN Buffer and Resultant Gate Degradation in AlGaN/GaN HEMTs

In this work, we report a critical semi- ON-state drain stress voltage above which the gate current increases significantly and degrades permanently in AlGaN/GaN high electron mobility transistors (HEMTs). The observed critical voltage was found to be channel field-dependent by analyzing devices with different field plate lengths and passivation thicknesses, along with different gate–drain distances. Besides field dependence, the critical voltage was found to be carrier energy dependent by comparing the performance of devices subjected to semi- ON-state stress with devices under OFF-state stress. Experimentation on HEMTs with different buffer carbon doping variations revealed the degradation phenomenon to be a function of carbon doping in the GaN buffer. Furthermore, detailed electric field and electron temperature analysis revealed the drain edge to be a hot spot in accelerating interaction of hot electrons with traps in the GaN buffer leading to gate current degradation. A mechanism based on hot electron–buffer trap interaction-induced thermoelastic stress buildup and subsequent defect formation in the GaN buffer is proposed to explain the observed performance degradations. Observations such as a significant rise in channel temperature and accumulation of mechanical stress in the GaN buffer validate the proposed mechanism. Finally, the processes responsible for degradation lead to catastrophic failure of the device for longer stress times by the formation of cracks and pits in the GaN buffer, as validated by the postfailure field emission scanning electron microscopy (FESEM) analysis.

New Erratic Program Disturbance Mechanism of 2T-SONOS Embedded Nonvolatile Memory

We developed a 32 kB embedded nonvolatile memory (NVM) intellectual property (IP) using 2T-SONOS cells. Although SONOS cells possess intrinsic defect immunity, we discovered abnormal memory cell failure during the probe test of the IP. The major failed items are checkerboard (CKBD), inverse CKBD, and gate-with-source (G-S) disturbance at the erased state. The threshold voltage distributions and electrical failure analysis (FA) reveal that all major failures occurred because of an abnormally weak G-S disturbance immunity. In addition, the temperature dependency of the G-S disturbance implies that the failure mechanism is related to Co-spike rather than midgap trap-induced junction leakage. Although abnormal defects are not detected through physical FA, by using simple failure modeling and a process split test, we verified the root cause of a new type of erratic failure. The single-bit disturbance failure can be explained as electrons generated in the floating junction area being accelerated in the G-S stress mode, resulting in soft programming by the channel hot electron (CHE) injection mechanism.

Degradation of gate-recessed MOS-HEMTs and conventional HEMTs under DC electrical stress* *Project supported by the Laboratory Open Fund of Beijing Smart-chip Microelectronics Technology Co., Ltd and the National Natural Science Foundation of China (Grant No. 11690042), the Science Challenge Project, China (Grant Nos. TZ2018004 and 12035019), and the National Major Scientific Research Instrument Projects, China (Grant No. 61727804).

The performance degradation of gate-recessed metal–oxide–semiconductor high electron mobility transistor (MOS-HEMT) is compared with that of conventional high electron mobility transistor (HEMT) under direct current (DC) stress, and the degradation mechanism is studied. Under the channel hot electron injection stress, the degradation of gate-recessed MOS-HEMT is more serious than that of conventional HEMT devices due to the combined effect of traps in the barrier layer, and that under the gate dielectric of the device. The threshold voltage of conventional HEMT shows a reduction under the gate electron injection stress, which is caused by the barrier layer traps trapping the injected electrons and releasing them into the channel. However, because of defects under gate dielectrics which can trap the electrons injected from gate and deplete part of the channel, the threshold voltage of gate-recessed MOS-HEMT first increases and then decreases as the conventional HEMT. The saturation phenomenon of threshold voltage degradation under high field stress verifies the existence of threshold voltage reduction effect caused by gate electron injection.

APPLICATIONS OF TCAD SIMULATION SOFTWARE TO THE STUDY OF FLOATING-GATE DEVICE

The floating-gate device has become an established component of all electronic systems, especially Non-volatile memories in recent years. This paper produces a study for this device including the structure and operation (read, program/write and erase). A complete flow which uses ATHENA, ATLAS and DEVEDIT3D tools for 2D and 3D structure simulations including I-V characteristics, Channel Hot Electron Injection, and Fowler-Nordheim Tunnel simulations are performed in TCAD environment.

Research for Hot Carrier Degradation in N-Type Bulk FinFETs

In this paper, the effect of hot carrier injection on an n-bulk fin field-effect transistor (FinFET) is analyzed. The hot carrier injection method is applied to determine the performance change after injection in two ways, channel hot electron (CHE) and drain avalanche hot carrier (DAHC), which have the greatest effect at room temperature. The optimum condition for CHE injection is VG=VD, and the optimal condition for DAHC injection can be indirectly confirmed by measuring the peak value of the substrate current. Deterioration by DAHC injection affects not only hot electrons formed by impact ionization, but also hot holes, which has a greater impact on reliability than CHE. Further, we test the amount of drain voltage that can be withstood, and extracted the lifetime of the device. Under CHE injection conditions, the drain voltage was able to maintain a lifetime of more than 10 years at a maximum of 1.25 V, while DAHC was able to achieve a lifetime exceeding 10 years at a 1.05-V drain voltage, which is 0.2 V lower than that of CHE injection conditions.

Unsupervised Learning by Spike-Timing-Dependent Plasticity in a Mainstream NOR Flash Memory Array—Part I: Cell Operation

This article and its part II demonstrate the possibility to operate a mainstream NOR Flash memory array as an artificial synaptic array learning without external supervision according to the spike-timing-dependent plasticity (STDP) rule. As a first mandatory step to this aim, suitable array working conditions allowing not only selective cell programming but also selective cell erase are here identified, overcoming the block erase operation typical of any Flash memory technology. The proposed array working conditions exploit channel hot-electron injection and hot-hole injection at the drain side to achieve selective, bidirectional, and virtually analog tuning of cell threshold voltage, with no need for changes in the design of a common-ground double-polysilicon NOR array. In part II, the new working scheme will be shown to allow for a straightforward implementation of STDP and unsupervised learning in the array.

Quantitative correlation between Flash and equivalent transistor for endurance electrical parameters extraction

Nowadays, the study of physical mechanisms that occur during Flash memory cell life is mandatory when reaching the 40 nm and beyond nodes in terms of reliability. In this paper we carry out a complete experimental method to extract the floating gate potential evolution during the cell aging. The dynamic current consumption during a Channel Hot Electron operation for a NOR Flash is a proper quantitative marker of the cell degradation. Here both drain and bulk currents are measured and monitored throughout the endurance tests. We coupled these characteristics with quasi-static measurements to correlate the cell degradation with an equivalent transistor. The final goal is to be able to split the physical effects of repetitive hot carrier and Fowler-Nordheim operations, typical of Flash memories, to extract the electrical parameters evolution on a simple equivalent transistor.

Trap state passivation improved hot-carrier instability by zirconium-doping in hafnium oxide in a nanoscale n-metal-oxide semiconductor-field effect transistors with high-k/metal gate

This work investigates the effect on hot carrier degradation (HCD) of doping zirconium into the hafnium oxide high-k layer in the nanoscale high-k/metal gate n-channel metal-oxide-semiconductor field-effect-transistors. Previous n-metal-oxide semiconductor-field effect transistor studies demonstrated that zirconium-doped hafnium oxide reduces charge trapping and improves positive bias temperature instability. In this work, a clear reduction in HCD is observed with zirconium-doped hafnium oxide because channel hot electron (CHE) trapping in pre-existing high-k bulk defects is the main degradation mechanism. However, this reduced HCD became ineffective at ultra-low temperature, since CHE traps in the deeper bulk defects at ultra-low temperature, while zirconium-doping only passivates shallow bulk defects.

Band-to-Band Hot Hole Erase Mechanism of p-Channel Junctionless Silicon Nanowire Nonvolatile Memory

In this paper, p-channel junctionless (JL) silicon-oxide–nitride-oxide–silicon (SONOS)-type nonvolatile memory (NVM) devices with gate-all-around (GAA) nanowire (NW) structure by using silicon-nanocrystal for the charge-trapping layer are presented. The devices exhibited good erase efficiency and excellent retention behavior and can be used in system-on-panel and 3-D-stacked flash memory applications. In addition, a band-to-band hot hole (BBHH) method for erasing is proposed and compared with the Fowler–Nordheim (FN) tunneling method. Because FN erasing requires a high gate voltage, BBHH erasing, which requires a low voltage, can increase the service life of the memory. Channel hot electron and band-to-band hot electron were used for programming and yielded low programming efficiency for the p-channel JL GAA NW NVM devices because of a lack of electron carriers. The program/erase efficiency is related to the channel type in JL NVM devices.

Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks

This work investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors (n-MOSFETs) with high-k/metal gate stacks. Many groups have proposed new models (i.e., single-particle and multiple-particle process) to well explain the hot carrier degradation in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO2 interface. However, for high-k dielectric devices, experiment results show that the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks.

Comprehensive study of hole injection in non-overlapped implantation n-type MOSFETs

The promising use of non-overlapped implantation (NOI) n-type MOSFETs as nonvolatile memory (NVM) devices has received considerable interest owing to their simple device structure and compatibility with logic CMOS processing. In NOI n-type MOSFETs, the charge distribution by channel hot electron injection (CHEI) programming markedly differs from that in other charge trapping devices in terms of electron injection distribution. In this study, hot hole injection (HHI) in NOI NVM devices is investigated using Technology Computer Aided Design (TCAD) simulations, measured program/erase speeds, and charge pumping (CP) techniques. Furthermore, HHI efficiency is theoretically deduced and compared with that of silicon–oxide–nitride–oxide–silicon (SONOS) devices. Similar to the results for SONOS device, the lateral fields by VD biases significantly enhance HHI for erasing NOI devices. However, preprogrammed electrons are also dominant in erasing NOI devices. On the basis of the CP results, the hole distribution by HHI in NOI NVM devices strongly correlates with the distribution of preprogrammed electrons.

Impact of endurance degradation on the programming efficiency and the energy consumption of NOR flash memories

In this paper the impact of the endurance degradation on the programming window and the energy consumption of flash floating gate memories is investigated. Using a new measurement technique we characterized the evolution of the dynamic drain current during the channel hot electron programming through the cycling. This experimental method has been developed for 90nm technology node flash floating gate memories, but it is fully compatible with the highly scaled devices. We define the programming efficiency as a new figure of merit to evaluate the performances of flash memories and we demonstrate why this decreases during the cell aging. Moreover we confirm that the efficiency optimization point varies with the cell degradation. Finally, with a complete set of measurements, we show that our experimental protocol enables the understanding of the role of defects generation on the programming efficiency of NOR flash memories for embedded low energy applications.

High Performance of Fin-Shaped Tunnel Field-Effect Transistor SONOS Nonvolatile Memory With All Programming Mechanisms in Single Device

This paper demonstrates a silicon-oxide-nitrideoxide-silicon (SONOS) nonvolatile memory (NVM) with fin-shaped polycrystalline silicon channel tunnel field-effect transistor (TFET). It differs from other memory devices in that its programming mechanisms include Fowler-Nordheim (FN) tunneling, channel hot-electron (CHE) injection, and band-to-band tunneling-induced hot electron (BBHE) in single memory cell. In FN programming, both the ON-state current and the program/erase (P/E) operations are based on quantum tunneling. For FN tunneling, when a V \(_{{{\rm G}}}\) of 17 V is applied for only 1 ms, this device has a large threshold voltage shift ( \(\Delta V_{\mathrm {\mathbf {TH}}}\) ) of 4.7 V. The fin-shaped TFET SONOS (T-SONOS) NVM exhibits superior endurance of 88% after 104 P/E cycles. The memory window remains 65% of its original value after 10 years at a high temperature of 85 °C. On the other hand, the device exhibits better endurance of 74% for CHE programming and BBHE programming after 104 P/E cycles. The memory window retains 81% in CHE programming and 65% in BBHE programming after 10 years. The fin-shaped T-SONOS NVM exhibits high performance that can be achieved in polycrystalline silicon NVM.

Electrical Characteristics of the Uniaxial-Strained nMOSFET with a Fluorinated HfO₂/SiON Gate Stack.

The channel fluorine implantation (CFI) process was integrated with the Si3N4 contact etch stop layer (SiN CESL) uniaxial-strained n-channel metal-oxide-semiconductor field-effect transistor (nMOSFET) with the hafnium oxide/silicon oxynitride (HfO2/SiON) gate stack. The SiN CESL process clearly improves basic electrical performance, due to induced uniaxial tensile strain within the channel. However, further integrating of the CFI process with the SiN CESL-strained nMOSFET exhibits nearly identical transconductance, subthreshold swing, drain current, gate leakage and breakdown voltage, which indicates that the strain effect is not affected by the fluorine incorporation. Moreover, hydrogen will diffuse toward the interface during the SiN deposition, then passivate dangling bonds to form weak Si-H bonds, which is detrimental for channel hot electron stress (CHES). Before hydrogen diffusion, fluorine can be used to terminate oxygen vacancies and dangling bonds, which can create stronger Hf-F and Si-F bonds to resist consequent stress. Accordingly, the reliability of constant voltage stress (CVS) and CHES for the SiN CESL uniaxial-strained nMOSFET can be further improved by the fluorinated HfO2/SiON using the CFI process. Nevertheless, the nMOSFET with either the SiN CESL or CFI process exhibits less charge detrapping, which means that a greater part of stress-induced charges would remain in the gate stack after nitrogen (SiN CESL) or fluorine (CFI) incorporation.