Abstract
The channel fluorine implantation (CFI) process was integrated with the Si3N4 contact etch stop layer (SiN CESL) uniaxial-strained n-channel metal-oxide-semiconductor field-effect transistor (nMOSFET) with the hafnium oxide/silicon oxynitride (HfO2/SiON) gate stack. The SiN CESL process clearly improves basic electrical performance, due to induced uniaxial tensile strain within the channel. However, further integrating of the CFI process with the SiN CESL-strained nMOSFET exhibits nearly identical transconductance, subthreshold swing, drain current, gate leakage and breakdown voltage, which indicates that the strain effect is not affected by the fluorine incorporation. Moreover, hydrogen will diffuse toward the interface during the SiN deposition, then passivate dangling bonds to form weak Si-H bonds, which is detrimental for channel hot electron stress (CHES). Before hydrogen diffusion, fluorine can be used to terminate oxygen vacancies and dangling bonds, which can create stronger Hf-F and Si-F bonds to resist consequent stress. Accordingly, the reliability of constant voltage stress (CVS) and CHES for the SiN CESL uniaxial-strained nMOSFET can be further improved by the fluorinated HfO2/SiON using the CFI process. Nevertheless, the nMOSFET with either the SiN CESL or CFI process exhibits less charge detrapping, which means that a greater part of stress-induced charges would remain in the gate stack after nitrogen (SiN CESL) or fluorine (CFI) incorporation.
Highlights
According to the international technology roadmap of semiconductors (ITRS), the equivalent oxide thickness (EOT) of the gate stack for metal-oxide-semiconductor field-effect transistors (MOSFETs) has to be scaled gradually to fulfill and increase device performance [1]
The fluorine atoms have been implanted into a silicon substrate before the dielectric deposition, the result obviously indicates that fluorine can be out-diffused from the substrate and effectively incorporated into the HfO2/silicon oxynitride (SiON) gate stack during the subsequent high temperature process, which is helpful for passivating the oxygen vacancies to form stronger Hf-F bonds, and reducing charge trapping [28]
The detrapping charges (Qdetrap), which are extracted from the VTH shift during the detrapping period, for the SiN CESL-strained n-channel metal-oxide-semiconductor field-effect transistor (nMOSFET) are less than the control device, implying that a larger part of the constant voltage stress (CVS)-induced charges would remain in the gate stack after nitrogen or fluorine incorporation
Summary
According to the international technology roadmap of semiconductors (ITRS), the equivalent oxide thickness (EOT) of the gate stack for metal-oxide-semiconductor field-effect transistors (MOSFETs) has to be scaled gradually to fulfill and increase device performance [1]. High-permittivity (high-k) metal oxides are thought to be gate dielectric materials for silicon (Si)-based devices, since a larger physical thickness than silicon dioxide (SiO2) or silicon oxynitride (SiON) can be utilized to reduce gate leakage current by suppression of direct tunneling, while maintaining required specific gate capacitance [2,3,4,5,6] For these reasons, various high-k dielectrics, including yttrium oxide (Y2O3), zirconium oxide (ZrO2), lanthanum oxide (La2O3) and hafnium oxide (HfO2) have been extensively studied as alternative gate dielectrics [2,3,4,5,6,7,8]. In this paper, fluorine incorporation using the CFI process has been used to comprehensively evaluate the electrical performance and device reliability of the SiN CESL uniaxial-strained nMOSFET with the fluorinated HfO2/SiON gate stack, which is expected to reduce VTH shift during both CVS and CHES, while maintaining a high drain current. With a fluorinated HfO2/SiON gate stack using the channel fluorine implantation (CFI) process
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