Modeling of Classical Channel Hot Electron Degradation in n-MOSFETs Using TCAD

Abstract

A technology CAD (TCAD) setup is used to calculate the channel hot electron (CHE) induced parametric drift in n-MOSFETs. The setup uses reaction-diffusion-drift model and utilizes carrier energy, vertical electric field, and lattice temperature effects, to calculate the time kinetics of trap generation and its impact on the device parametric drift. Experimental data from published reports, measured using different probes, for midgate bias stress under varying drain bias ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 3$ </tex-math></inline-formula> –8 V) and temperature (0 °C–100 °C) are modeled, in classical devices having different channel lengths (2.0– <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.3~\mu \text{m}$ </tex-math></inline-formula> ) and oxide thicknesses (35–5 nm). The impact of device dimension scaling on the spatial distribution of generated traps and their impact on the device parametric drift are discussed.