Inverter Chain Research Articles

An Enhanced LPRAFF with Tri-State Inverter Embedded Non-Clock Gating via the CT-GWO Algorithm

Since a long time ago, it has been understood how radiation affects digital circuits, particularly those using the Complementary Metal Oxide Semiconductor (CMOS) model. Total Ionisation Dose (TID) and Single Event Effects (SEE) are the two most significant radiation effects. Depending on the gate input count, the complexity of the circuit will rise, which will worsen the radiation and raise the cumulative dose levels. The incremental dose level affects the circuit parameter failure, which affects how well the logic design functions. Many authors concentrate on minimising the effects of radiation while preventing function loss, but these extra efforts use excess energy. To improve the efficiency of the Low Power Radiation Aware (LPRA) circuit, this paper introduces optimisation concepts in a Flip Flop (FF) architecture named Chaos Theory-based Grey Wolf Optimised FF (CT-GWOFF). First, compute each component's radiation response using a physics-based modelling strategy. To minimise undesirable latches and disable the inverter chain when the input data remain constant, a tri-state inverter, incorporating a non-clocked gating mechanism, is provided. This prevents repeated transitions of delayed clock signals. Moreover, the proposed model is implemented in FFs for simulation purposes, making it more cognizant of radiation effects and power consumption. Using the HSPICE tool, the performance of the suggested circuit design is evaluated at the 16 nm CMOS Predictive Technology Model (PTM).

Circuits implementations using carbon nanotube field-effect transistor nanotechnology

Device scaling is a pivotal aspect in the field of electronics, aimed at enhancing the performance of integrated circuits (ICs) by reducing the dimensions of transistors. The device scaling presents the short channel effects (SCEs) in the nanoscale regime. To address the SCEs, nanometer IC designers have turned to the carbon nanotube field-effect transistor (CNTFET) technology, which offers unique properties and mitigates the challenges associated with transistor scaling. In this research work, a leakage reduction technique known as the input-dependent (INDEP) method is suggested to tackle the leakage current issue at the nanoscale regime using CNTFET technology. The INDEP method involves the incorporation of two additional transistors within the logic circuit. To evaluate the efficacy of the INDEP method, a CNTFET-based 7-stage inverter chain is meticulously designed at 32 nm CNTFET technology node. Subsequent comparative analysis against alternative designs is conducted, assessing performance metrics such as power dissipation, delay, and power delay product (PDP). The suggested INDEP method reduces power dissipation by 83.75% and improves PDP by 78.44%. Furthermore, the study delves into the impact of process, voltage, and temperature (PVT) variations. Additionally, the investigation explores the influence of parameters such as the number of carbon nanotubes, temperature, supply voltage, and chiral indices on the performance of the 7-stage inverter chain. The simulation results demonstrate that the CNTFET-based INDEP technique yields promising outcomes, characterized by low power dissipation, precise output, and minimal uncertainty across all evaluated metrics.

Using Memristor Element to Improve the Reliability of Digital Circuits

Memristor has been used as a filter stage to improve The reliability of digital circuits has been improved by using memristor. This element works as a filter stage to waive most of the glitches generated in prior stages. The proposed technique is applied to three different circuits to improve their reliability. Those circuits are: a chain of inverters represents a long path topology, c432 benchmark represents a short path circuit, c1908 benchmark represents a long path circuit. The memristor stage is connected between the last two stages of each output path of the circuit. The memristance of the memristor is changed using a certain parameter (x0), higher memristance means longer propagation delay and more glitches are attenuated. The experiment is run at different values of the memristance and the error probability is calculated at each value. The effect of this stage is studied by calculating the energy consumption and performance of the circuits with and without this stage. The Reliability-Energy-Performance trade-off relationship is found and introduced for each circuit, the results show that the reliability of the circuit is improved to the highest levels, when

A capacitive mismatch calibration method for SAR ADCs based on TDC

AbstractThe capacitance mismatch problem limits the accuracy improvement of high‐precision SAR ADCs (Successive Approximation Register Analog‐to‐Digital Converters). To address the capacitance array mismatch in SAR ADCs, this paper proposes a novel capacitor calibration scheme based on the Time‐to‐Digital Converter (TDC). This scheme achieves calibration accuracy as high as 0.01% and can be flexibly designed to meet the accuracy requirements of SAR ADCs. Simulation results indicate that the capacitance mismatch issue of a redundant capacitor 13‐bit SAR ADC can be completely eliminated, and the effective number of bits (ENOB) approach the ideal value of 13.18 bits. Additionally, the analog component of this scheme utilizes four inverter chains, two D flip‐flops, and four counters, without requiring a large area for auxiliary calibration capacitors.

Analysis of Single-Event Upsets and Transients in 22 nm Fully Depleted Silicon-On-Insulator Logic

In this work, single-event upset (SEU) and single-event transient (SET) responses of digital logic in a planar 22nm fully-depleted conventional-well silicon-on-insulator (FD-SOI) technology under various test conditions are presented. The D-flip-flop (DFF) shift registers used for the single-event upset experiments are more sensitive to upsets when data is dynamically loaded in during irradiation rather than statically stored beforehand, but the clock rate used to load the data does not affect the upset cross sections in any significant way. The digital pattern loaded also affects the upset cross sections, but which cross section is greater between patterns of all “1s” and all “0s” is observed to be opposite for dynamic and static tests. A key capability of the technology studied in this work is the ability to apply biases to the back gates of transistors to alter threshold voltage. For conventional-well designs, as in this work, reverse body bias can be applied, increasing the threshold voltage and decreasing leakage current. Analyzing the effects of applying a back-gate bias on single-event upset cross section reveals no clear trend for single-event upset cross sections in the D-flip-flop shift registers but applying back-gate bias decreased the single-event transient cross sections measured from an inverter chain by as much as an order of magnitude. Supplementary SPICE-level simulations suggest that the drastic decrease in single-event transient cross section results from attenuation in the inverter chain. The presented experimental and simulation results indicate relatively small single-event cross sections compared to other technologies reported in literature.

Heavy-ion and pulsed laser induced single-event double transients in nanometer inverter chain

Single-event double transients (SEDT) measurement in a designed 65-nm bulk CMOS inverter chain is performed under heavy-ion irradiation and pulsed laser irradiation. An SEDT event is observed under Ta ions irradiation, and it is found to result from the charge sharing between electrically connected inverters by TCAD simulation. Laser experimental results show that SEDT generation increases with the laser pulse energy as well as the supply voltage of the inverter chain. The pulse width distributions of SEDT for the laser irradiations of different rows demonstrate that SEDT events generated far from the chain output are modified by the pulse broadening during propagation: the first and second single-event transients are broadened, but the temporal differences are shrunk. The difference of SEDT cross-sections between the laser irradiations of different rows suggests that SEDT may be mitigated by controlling propagation.

Prediction of Power Supply Induced Jitter With PDN Design Parameters

This article proposes a method to predict power supply induced jitter (PSIJ) at the inverter chain buffer output with the design parameters of power distribution network (PDN). The PDN is assumed to contain multiple decoupling capacitors with sufficiently different values for each branch. The relationship between PSIJ and PDN design parameters is derived analytically by convoluting the time-domain voltage ripple with the buffer time-domain PSIJ sensitivity, given the triangular noise current information. The analytical formula is validated through measurement by using an in-house designed CMOS buffer circuit and a controllable aggressor circuit based on 180 nm technology. The buffer output PSIJ under the operation of the aggressor circuit and the corresponding switching noise current are characterized. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R–L–C</i> design parameters of PDN are extracted through impedance measurement. With the PDN parameters, the output jitter is calculated with the derived formulation. Compared with the measurements, the prediction error of the proposed method is within 8.1% when the voltage ripple amplitude is no larger than 10% of the supply voltage.

Effect of temperature on heavy ion-induced single event transient on 16-nm FinFET inverter chains

The variations of single event transient (SET) pulse width of high-LET heavy ion irradiation in 16-nm-thick bulk silicon fin field-effect transistor (FinFET) inverter chains with different driven strengths are measured at different temperatures. Three-dimensional (3D) technology computer-aided design simulations are carried out to study the SET pulse width and saturation current varying with temperature. Experimental and simulation results indicate that the increase in temperature will enhance the parasitic bipolar effect of bulk FinFET technology, resulting in the increase of SET pulse width. On the other hand, the increase of inverter driven strength will change the layout topology, which has a complex influence on the SET temperature effects of FinFET inverter chains. The experimental and simulation results show that the device with the strongest driven strength has the least dependence on temperature.

Characterization of charge sharing induced by high LET heavy ions using inverter chains in a commercial bulk FinFET process

The inverter is one of the most important cell types in any standard cell library at each technology node, and it is also very important for single-event research. The distributions and cross-sections of single-event transients (SETs) and single-event multiple transients (SEMTs) were characterized using 14/16 nm bulk fin field-effect transistor (FinFET) inverters under heavy ion radiation. An inverter with double driving strength (INVX2) was used as an instantiate object to observe the SET and SEMT response. 181Ta with energies of 1891 GeV and 2000.5 MeV were used respectively in the experiments, of which the linear energy transfer (LET) values were 87.4 MeV cm2 mg−1 and 75.4 MeV cm2 mg−1. The test results indicated that: (a) the mean pulse widths of the SET and SEMT were less than 100 ps, and decreased with LET decreasing; (b) there was charge sharing between abutted INVX2 inverters placed horizontally, and the generation probability of SEMT induced by charge sharing was less than 1% even if the LET of heavy ion reached 87.4 MeV cm2 mg−1. The results were beneficial for a better understanding of SET and SEMT tolerance for inverters in FinFET technology.

The Performance Enhancement of PMOSFETs and Inverter Chains at Low Temperature and Low Voltage by Removing Plasma-Damaged Layers

In this work we report on the improvement in cold temperature characteristics of PMOSFETs and inverter circuits by removing the plasma-damaged layer of the source/drain contacts. We removed the plasma-induced damage on the Si using a simple in situ Si soft treatment technique. We found by transmission electron microscope (TEM) analysis that the damaged amorphous layer reduced from 52 Å to 42 Å and 35 Å with a treatment time of 10 and 20 s, respectively. As a result, the resistances of both the n+ and p+ contacts decreased for all contact sizes and the standard deviations at the cold temperature were suppressed by 45%. At −25 °C, the saturation current of the PMOSFET increased by 3% and the propagation delay time (tPD) decreased by 2%. The tPD increases by 19.3% when the temperature decreases from 85 °C to −25 °C, and the operating voltage decreases from 1.2 V to 0.95 V at the same time. However, this increase can be reduced to 17% by applying the soft treatment for 10 s. This simple and short time process will be considered essential for both mobile applications and automotive applications of dynamic random access memory (DRAM) devices requiring a low-voltage and low-temperature operation.

ЛОГИЧЕСКАЯ ЯЧЕЙКА ДЛЯ СБИС НА ОСНОВЕ ПОЛЕВЫХ ТРАНЗИСТОРОВ С P-N-ПЕРЕХОДАМИ

In the 80s of the last century, integrated injection logic (I2L) was widely used as an elementbase. Somewhat later, injection-field logic (IPL) appeared in the development of I2L capabilitiesfor building VLSI. Thanks to the use of a field-effect transistor as a key element of the inverter, inthis element basis it was possible to significantly reduce an important indicator for VLSI – powerconsumption - reaching the peak-watt range. An even greater reduction in power consumption canbe achieved by using two field-effect transistors in the inverter unit cell, which is proposed in thispaper. This element basis is proposed to be called field-field logic, or in the future P2L. To reducethe dimensions of the P2L cell, field-effect transistors, both key and load, are made with a verticalchannel. In addition, to ensure a positive supply voltage, an n-channel transistor is used as a keyone, and a p–channel transistor is used as a load one. Both transistors are normally closed, i.e.closed at zero gate voltage. Topological variants of P2L-cell execution from geometry with annulargates to geometry with linear gates proposed by the author earlier are considered. The topologicalnorms adopted in the consideration are the norms of 50 nm. The power consumption in thiselement basis is reduced by about two times compared to the IPL, due to the fact that the currentflows through the load transistors in the inverter chain through one inverter, as well as throughthe key ones. The technological process of manufacturing a P2L cell is considered, the profiles ofthe distribution of impurities in depth are calculated. The manufacturing process is designed takinginto account the fact that the load p-channel transistor must be made in an insulated pocketusing full dielectric insulation technology. The technological modes of manufacturing the P2L cellare given. The proposed design and technological variant of the P2L cell can be recommended forthe creation of VLSI with low power consumption.

Negative capacitance based phase-transition FET for low power applications: Device-circuit co-design

In this article, we have performed a comprehensive study into the Phase Transition Material based FinFET(PT-FinFET) device’s capabilities for low-power, energy-efficient applications through device circuit co-design perspective. Addressing its drawback at device and circuit level a novel device design known as the Negative Capacitance Phase Transition FinFET(NC-PTFinFET) is proposed by incorporating a ferroelectric material layer into the gate stack of the PTFinFET. The proposed device outperforms PTFinFET and FinFET in terms of SS and ON–OFF current ratio at the device level, as well as power and speed at the circuit level, and provides device tunability. With three case studies of embedded inverter chain, RO, and 2-bit RCA it was observed that the proposed NC-PTFinFET shows performance benefits in speed by reducing delay in these circuits with increasing NC thickness in comparison with the PTFinFET and FinFET. In contrast, increasing NC thickness in the proposed device energy efficiency is improved as compared to PTFinFET and FinFET.

Measuring and Modeling Single Event Transients in 12-nm Inverters

In this article, we present a unique method of measuring single-event transient (SET) sensitivity in 12-nm FinFET technology. A test structure is presented that approximately measures the length of SETs using flip-flop shift registers with clock inputs driven by an inverter chain. The test structure was irradiated with ions at linear energy transfers (LETs) of 4.0, 5.6, 10.4, and 17.9 MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg, and the cross sections of SET pulses measured down to 12.7 ps are presented. The experimental results are interpreted using a modeling methodology that combines TCAD and radiation effect simulations to capture the SET physics, and SPICE simulations to model the SETs in a circuit. The modeling shows that only ion strikes on the fin structure of the transistor would result in enough charge collected to produce SETs, while strikes in the subfin and substrate do not result in enough charge collected to produce measurable transients. Comparisons of the cumulative cross sections obtained from the experiment and from the simulations validate the modeling methodology presented.

Characterization of single-event transients induced by high LET heavy ions in 16 nm bulk FinFET inverter chains

Single-event transient (SET) distributions and cross-sections are characterized for 16 nm bulk FinFET inverters with different threshold voltages and driving strengths using the heavy ion 181Ta with the energy of 1.07GeV and the Linear Energy Transfer (LET) of 85 MeV·cm2/mg. Lower threshold voltage makes shorter SET pulses and smaller cross-section, and reduces the upper limit of the SET pulse width, which is advantageous to harden the FinFET gates against the high LET heavy ion irradiation. Enhancing the driving strength changes the layout topology, leading to complicated impact on the radiation sensitivity for FinFET inverters. The source region is laid at one side of the drain region in P or N type transistor of the inverter with driving strength X1 (INV1), while there are two source regions at both sides of the drain region in P or N type transistor in the inverter with driving strength X2 (INV2), which makes INV2 is more SET tolerant than INV1. There are interdigitated two drain regions and three source regions in P or N type transistor of the inverter with driving strength X4 (INV4), which expands the sensitive area and cross-section. The test results indicate that the max SET pulse width is approximately proportional to the ratio of sensitive area to driving strength for the FinFET inverters, that is the max SET pulse width of INV4 is between INV1 and INV2.

Impact of single event transient effect on adiabatic logic circuits

The evolution of the modern Complementary Metal Oxide Semiconductor technology has led to the scaling of the transistor size to nanometers. This has resulted in significant benefits to integrated circuits, such as higher speed, smaller circuit size and lower operating voltage. However, this smaller size and lower operating voltage have become highly susceptible to operational disturbances such as signal coupling, substrate noise, and single event effects caused by ionizing particles. Single Event Transient occurs when a high-energy particle strikes a combinational logic circuit. The charge deposited by the particle causes a transient voltage disturbance to load incorrect data. In this work, the impact of Single Event Transient on total power dissipation and the delay of static complementary logic is analyzed. Different circuits like basic inverter, adiabatic inverter, chain of inverters of complementary and adiabatic logic have been selected for the analysis. The technology node used for this analysis is 180 nm and 90 nm using Cadence Virtuoso. The result shows that on scaling, the effect of Single Event Transient is increased, and the use of an adiabatic logic reduces the power by 15% compared to conventional static logic circuits.

String Stability in Microgrids Using Frequency Controlled Inverter Chains

In this letter we identify, and propose a solution for, the string stability problem that may arise in frequency droop control schemes for a type of inverter-based microgrid. We consider a previously proposed frequency droop control with secondary control loop and we investigate the effect on the performance due to an increase in the number of inverters connected to the microgrid. To mitigate the observed performance deterioration, we propose a new controller that guarantees string stability of the inverter-based microgrid and show its performance via simulations.

Insights into the operation of negative capacitance FinFET for low power logic applications

In the incessant search to overcome the power densities and energy efficient limitations, performance matrix of emerging electronic devices are being explored inevitably to find the alternatives of MOSFETs. We investigated and compared the delay and energy performance matrices of fin-shaped FET and negative capacitance FinFET (NC-FinFET) based devices and circuits designed on the same technology node. The improvement in the performance of NC-FinFET based CMOS circuits is enhanced due to the negative capacitance’s negative DIBL by employing a industry standard BSIM-CMG model. After analyzing at the device-level, detailed evaluation is carried out at logic level for embedded inverter chain, three-stage ring oscillators (ROs), and 2-bit ripple carry adders (RCA) for frequencies ranging between 10 kHz–1 GHz. Our findings revealed that the NC-FinFET based circuit has a lower delay for a given range of operating frequencies and saves a significant amount of power when compared to baseline FinFET, making NC-FinFET desirable for low power digital logic applications.

Synthesis of Low-Voltage Logic Gates on Surrounding Gate SOI CMOS Nanotransistors

We discuss the issues of synthesis of low-voltage logic gates on cylindrical surrounding gate SOI CMOS nanotransistors in the supply voltage range up to 0.8 V. In this transistor architecture, it becomes possible to more effectively control the charge in its working area, primarily due to its design parameters. It is also characterized by effective suppression of short-channel effects and a low capacitance value. This leads to a decrease in the level of power dissipation in combination with a reduction in the occupied area. TCAD models of n- and p-types nanotransistors have been developed. The anomalous behavior of the dependence of the threshold voltage on the diameter of the working area is revealed, which is associated with the peculiarities of the manifestation of short-channel effects due to the capacitive interaction of the gate-channel regions and drain-source transitions at small gate lengths. They were used to select prototypes of transistors with optimal parameters for the synthesis of complex logic gates with low supply voltage. Using the mathematical core of the HSPICE program, the dynamic characteristics of the developed physical models of the inverter, the inverter chain, and the XOR2 are numerically investigated. At control voltages of 0.8 V and a frequency of 50 GHz, the inverter model predicts a maximum switching delay of 3.3 ps, a limit level of active power of 1.1 mkW, static 0.3 pW, the XOR2 predicts a maximum switching delay of 8.6 ps, a limit level of active power of 4.9 mkW, static 1.5 pW. The minimum of the product "delay * power" of the adder is at a supply voltage of 0.72 V. Its position does not depend on the set of input signals. At the same time, the maximum switching delay is 10.8 ps, the maximum active power level is 3.9 mkW. The totality of the obtained characteristics allows us to consider the analyzed transistor architecture for creating low-power electronic devices.

Effect of Cell Placement on Single-Event Transient Pulse in a Bulk FinFET Technology

In this article, five different cell placement structures of a vertical inverter chain were designed in a commercial bulk FinFET technology to investigate the effect of cell placement on a single-event transient (SET) pulse. 3-D TCAD mixed-mode simulation indicated that the cell placement has a significant effect on SET pulsewidths. Heavy-ion experiments at Cyclotron in the China Institute of Modern Physics in Lanzhou also indicated that the effect of cell placement on the SET pulse is obvious. The experiment also indicated that the effect of cell placement on P-hit SET is larger than that on N-hit SET, and charge sharing in vertical was becoming as important as that in horizontal.

Relationship between ion track characteristics and single event transients in nanometer inverter chain

Ions with the same linear energy transfer (LET) value, but different energies and species have various ion track characteristics, and thus induce different single event transient (SET) responses in combinational logics. As the technology feature size shrinks, this issue continues to be serious. The research of the relationship between ion track characteristics and SETs in the nanometer combinational logic circuits is of great significance for accurately predicting the soft error rates of nanometer devices used in spacecraft. The combinational logic circuit investigated in this paper is a 65 nm bulk silicon complementary metal oxide semiconductor (CMOS) technology inverter chain. The three-dimensional TCAD model of the inverter chain is established, and the particle transport program for the ion track in bulk silicon is developed by Geant4. The track characteristics of high- and low-energy ions (the energy of low-energy ions is less than 10 MeV·n&lt;sup&gt;–1&lt;/sup&gt;, the energy of high-energy ions ranges from tens of MeV·n&lt;sup&gt;–1&lt;/sup&gt; to hundreds of MeV·n&lt;sup&gt;–1&lt;/sup&gt;) which have the same LET value are compared with each other. Based on the coupled simulation of TCAD and Geant4, the difference in SET pulse widths, induced by ions with the same LET value but different energies, are investigated. It is found that when the energy per nucleon ratio of high-energy ion to low-energy ion increases, the difference in electron-hole pair densities near the center axis of the ion track is more significant, and thus the difference in SET pulse widths is larger. If the energy per nucleon ratio is similar, raising the LET value of ions can increase the difference in electron-hole pair densities on the same radial scale of the ion tracks, and make the SET pulse width difference more obvious. For the high- and low-energy ions with the same LET value, the single event charge generations are different. On the other hand, the change of the ion incident angle results in different charge collections. The coupling of these two factors makes the difference in SET pulse widths dependent on the incident angle of ions. In addition, the influence of ion track characteristics on SET has a weak correlation with the bias voltage of the inverter chain.