Impact of single event transient effect on adiabatic logic circuits

Abstract

The evolution of the modern Complementary Metal Oxide Semiconductor technology has led to the scaling of the transistor size to nanometers. This has resulted in significant benefits to integrated circuits, such as higher speed, smaller circuit size and lower operating voltage. However, this smaller size and lower operating voltage have become highly susceptible to operational disturbances such as signal coupling, substrate noise, and single event effects caused by ionizing particles. Single Event Transient occurs when a high-energy particle strikes a combinational logic circuit. The charge deposited by the particle causes a transient voltage disturbance to load incorrect data. In this work, the impact of Single Event Transient on total power dissipation and the delay of static complementary logic is analyzed. Different circuits like basic inverter, adiabatic inverter, chain of inverters of complementary and adiabatic logic have been selected for the analysis. The technology node used for this analysis is 180 nm and 90 nm using Cadence Virtuoso. The result shows that on scaling, the effect of Single Event Transient is increased, and the use of an adiabatic logic reduces the power by 15% compared to conventional static logic circuits.