An Enhanced LPRAFF with Tri-State Inverter Embedded Non-Clock Gating via the CT-GWO Algorithm

Abstract

Since a long time ago, it has been understood how radiation affects digital circuits, particularly those using the Complementary Metal Oxide Semiconductor (CMOS) model. Total Ionisation Dose (TID) and Single Event Effects (SEE) are the two most significant radiation effects. Depending on the gate input count, the complexity of the circuit will rise, which will worsen the radiation and raise the cumulative dose levels. The incremental dose level affects the circuit parameter failure, which affects how well the logic design functions. Many authors concentrate on minimising the effects of radiation while preventing function loss, but these extra efforts use excess energy. To improve the efficiency of the Low Power Radiation Aware (LPRA) circuit, this paper introduces optimisation concepts in a Flip Flop (FF) architecture named Chaos Theory-based Grey Wolf Optimised FF (CT-GWOFF). First, compute each component's radiation response using a physics-based modelling strategy. To minimise undesirable latches and disable the inverter chain when the input data remain constant, a tri-state inverter, incorporating a non-clocked gating mechanism, is provided. This prevents repeated transitions of delayed clock signals. Moreover, the proposed model is implemented in FFs for simulation purposes, making it more cognizant of radiation effects and power consumption. Using the HSPICE tool, the performance of the suggested circuit design is evaluated at the 16 nm CMOS Predictive Technology Model (PTM).