Ceramic Ball Grid Array Research Articles

Foreword contributions from the 1998 intersociety conference on thermal and thermomechanical phenomena in electronic packages

HE Thermomechanical analysis of electronic packages is a critical aspect of reliability assessment. Although the focus of earlier Intersociety Conferences on Thermal and Thermomechanical Phenomena in Electronic Packages (ITherm) was on thermal analysis, thermomechanical issues that ensue from thermally-induced strains and stresses are receiving increased attention at the Conference. ITherm has been making steady progress in terms of quantity and quality of papers in this area over the years and we expect it to hold for ITherm 2000. In this special section of this TRANSACTIONS ,w e showcase outstanding papers that were presented at ITherm 98 on thermomechanical issues related to electronic packaging. Seven papers are selected for this special issue based on a rigorous review process. The majority of the papers deal with various aspects of the solder joint reliability, mainly in the flip-chip ball grid array (BGA) packages. Based on a parametric study of the effect of voids in the underfill of a ceramic BGA, Niu et al. have concluded that the edge voids decrease C4 fatigue life where as middle and center voids have less impact. A comparison of solder joint reliability for ceramic quad-flat-pack and CBGA packages for two typical accelerated temperature cycles (0 C to 100 C and 40 C to 125 C) of interest for microprocessors has been carried out by Gerke et al. They have also looked at the effect of temperature gradient on solder joint reliability by using experimentally measured temperatures. Bailey et al. have integrated the effect of fluid flow, heat transfer during solidification, and stress evolution on solder joint formation. Ayhan and Nied have applied enriched crack tip finite elements for prediction of interface fracture parameters. They have evaluated two-dimensional and three-dimensional models for moisture absorption and thermal cycling. Material properties and BGA model validation issues are addressed in the last three papers. Using a three-point bending test, Tay and Lin have measured the effect of temperature and moisture on interfacial fracture toughness for molded QFPs. They have also examined the effect of interfacial defect location of fixed initial size on interfacial crack growth. Tran et al. have characterized fracture toughness for various underfill materials for improved adhesion. Finally, Zhang et al. have Publisher Item Identifier S 1521-3331(99)10361-1. used a combined experimental and numerical approach to evaluate various material and geometric assumptions made in the analyses of area-array packages. We hope the papers presented here will add to the knowledge of predictive engineering. We wish to acknowledge the efforts of many individuals who helped with this special section on mechanics. We would like to thank all the reviewers for their tireless efforts in completing the reviews in a short period of time. In some cases, this involved two rounds of reviews. We would like to thank J. Starbird and K. Mauch of the Editor’s office for administrative assistance. Last, but not least, this effort would not have been possible but for the encouragement and guidance of Editor-in-Chief Avram Bar-Cohen.

The Effect of Solder Paste Volume and Reflow Ambient Atmosphere on Reliability of CBGA Assemblies

To investigate the effect of stencil thickness and reflow ambient atmosphere on the reliability of ceramic ball grid array (CBGA) assemblies, three levels of stencil thickness, 0.10, 0.15, and 0.20 mm, were used to print solder paste on printed circuit board (PCB). After the CBGA modules were placed on PCBs, the specimens were divided into two groups, and reflowed in nitrogen and compressed air separately. Properties of the six groups of assemblies, such as shear strength, bending fatigue life, thermal shock cycles, and vibration fatigue life, were tested to find out the optimum assembling process. The results show that assemblies prepared with a stencil 0.15 mm thick yield maximized performance. And the nitrogen ambient atmosphere demonstrates a remarkable effect on improving the fatigue life. Theoretical models are given to qualitatively explain the relationship between the solder joint volume and performance. This work provides a guideline on how to determine the soldering process parameters of CBGA assemblies.

Solder joint reliability of high I/O ceramic-ball-grid arrays and ceramic quad-flat-packs in computer environments: the PowerPC 603/sup TM/ and PowerPC 604/sup TM/ microprocessors

Recent trends in wafer fabrication techniques have produced devices with smaller feature dimensions, increasing gate count and chip inputs/outputs (I/Os). This trend has placed increased emphasis on microelectronics packaging. Surface-mountable packages such as the ceramic quad-flat-pack (CQFP) have provided solutions for many high I/O package issues. As the I/O count gets higher, the pitch has been driven smaller to the point where other solutions also become attractive. Surface-mountable ceramic-ball-grid array (CBGA) packages have proven to be good solutions in a variety of applications as designers seek to maximize electrical performance, reduce printed-circuit board real estate, and improve manufacturing process yields. In support of the PowerPC 603 and PowerPC 604 microprocessors, 21 mm CBGA (255 I/Os) and 32 mm (240 I/Os) and 40 mm (304 I/Os) CQFPs are being utilized. Both package types successfully meet computer environment applications. This paper describes test board assembly processes, accelerated thermal stress test setup, and solder joint failure criteria. Failure mechanisms for both packaging technologies will also be presented. The packages discussed in this paper were subjected to two accelerated thermal cycling conditions: 0 to 100/spl deg/C and -40 to 125/spl deg/C. The failure data are plotted using Weibull distributions. The accelerated failure distributions were used to predict failure distributions in application space for typical PowerPC 603 and PowerPC 604 microprocessors computer environments. To predict solder joint reliability of surface-mount technology, a key parameter is: the temperature rise above ambient at the solder joint, /spl Delta/T. In-situ field temperature measurements were taken for a range of computer platforms in an office environment, at the central-processing units. Printed-circuit boards (PCB) were not uniform, therefore only maximum temperature regions of the board were measured. These maximum temperatures revealed the mean to be less than 20/spl deg/C above ambient (i.e., /spl Delta/T<20/spl deg/C) regardless of the power of the device. The largest /spl Delta/T measured in any system was less than 30/spl deg/C above ambient. These temperature measurements of actual computer systems are in close agreement with IPC-SM-785. By utilizing the measured PCB temperature rise, solder joint fatigue life was calculated for the 21 mm ceramic ball-aid-array (CBGA), the package for the PowerPC 603/sup TM/ and PowerPC 604/sup TM/ RISC microprocessors. The average on-off /spl Delta/T for most computer applications is approximately 20/spl deg/C. For an average on-off /spl Delta/T of 30/spl deg/C, the 21 mm CBGA has an estimated fatigue life of over 25 years while the 32 mm and 40 mm CQFP's have an estimated fatigue life of over 50 years.

Ball grid array reliability assessment for aerospace applications

Reliability of ball grid arrays (BGAs) was evaluated with special emphasis on space applications. This work was performed as part of a consortium led by the Jet Propulsion Laboratory (JPL) to help build the infrastructure necessary for implementing this technology. Nearly 200 test vehicles, each with four package types, were assembled and tested using an experiment design. The most critical variables incorporated in this experiment were package type, board material, surface finish, solder volume, and environmental condition. The packages used for this experiment were commercially available packages with over 250 I/Os including both plastic and ceramic BGA packages. The test vehicles were subjected to thermal and dynamic environments representative of aerospace applications. Two different thermal cycling conditions were used, the JPL cycle ranged from −30°C to 100°C and the Boeing cycle ranged from −55°C to 125°C. The test vehicles were monitored continuously to detect electrical failure and their failure mechanisms were characterized. They were removed periodically for optical inspection, scanning electron microscopy (SEM) evaluation, and cross-sectioning for crack propagation mapping. Data collected from both facilities were analyzed and fitted to distributions using the Weibull distribution and Coffin–Manson relationships for failure projection. This paper will describe experiment results as well as those analyses.

A Two-Body Formulation for Solder Joint Shape Prediction

Solder shape prediction is essential for accurate fatigue life determination and joint design optimization. In the present paper, a new solution approach using the surface tension theory is developed to simultaneously predict standoff height, wetted surface area, contact angles, and solder shape by including energy effects between a molten solder body and an arbitrarily shaped solid body. Existing models for solder shape prediction do not appear to determine all characteristics including joint standoff height, wetted surface area, and contact angles simultaneously. A general two-body axisymmetric finite element code is developed and coupled with a constrained optimizer to solve four illustrative examples. These examples include the shape of a sessile droplet on a fixed pad, a flip-chip joint, a sessile droplet on a free surface, and a typical ceramic ball grid array solder joint. In all four examples, the results predicted by the present approach compare favorably with available experimental and numerical results.

Process capability study and thermal fatigue life prediction of ceramic BGA solder joints

The design and process capability of board-level assembly of ceramic ball grid array (CBGA) packages with respect to their reliabilities were investigated. Two types of FEM models were built for elastic and elastic–plastic–creep analyses, respectively. The effect of PCB material, PCB thickness, and the thickness of ceramic substrate on solder joint deformation was discussed. It was shown that the variation in assembly process would cause the highest stress in the joints change by 10% from the mean value. The failure location and fatigue life under the temperature cycling condition were also studied. It was concluded that the prediction was close to the first failure in the test and would be seen as a conservative estimation.

CBGA Solder Fillet Shape Prediction and Design Optimization

In this paper, we first present a mathematical method that can be used to predict the eutectic solder fillet shape for ceramic ball grid array joints. An underlying assumption is that the solder fillets on both the module and the card sides can be represented as arcs. The fillets’ profiles are then calculated for the factors affecting the shape including solder volume, pad size, solder ball size, the wetting angle between eutectic solder and solder ball, and the gap between solder ball and pad. The second part of the paper focuses on design for reliability and investigates the effect of the interactions between the card-side and the module-side solder fillets on CBGA solder joint reliability. To this end, a central composite design of experiment is set up to systematically vary the pad size and the eutectic solder volume on both the module and the card sides. For each of the design settings, the proposed mathematical method is used to calculate the solder fillet shape. Using ABAQUS and the modified Coffin-Manson relationship, the mean fatigue life is predicted. The implications of the simulations are discussed. In addition, a response surface model is presented to find the optimum settings for maximum reliability. Finally, a comparison is made for the fatigue life predictions obtained using the proposed mathematical method and the linear solder fillet assumption.

The Effect of Stencil Printing Optimization on Reliability of CBGA and PBGA Solder Joints

As a follow-up and conclusion to previous work in stencil printing process modeling and optimization (Li et al., 1996), we investigate the effect of stencil printing optimization on the reliability of the ceramic and plastic ball grid arrays. For ceramic ball grid arrays, the eutectic solder fillet shape is calculated using a series of simple mathematical equations. The thermal strain distributions within the solder joints after two cycles of accelerated thermal cycling test are estimated using three-dimensional finite element models. The modified Coffin-Manson relationship is applied to calculate the mean fatigue lives of the solder joints. The results reveal that an optimized stencil printing process significantly reduces variation in the fatigue life of ceramic ball grid arrays. The results also show that the fatigue life of ceramic ball grid arrays is very sensitive to the card-side solder volume. The maximum strain region shifts from the card-side eutectic solder to the module side as the card-side eutectic solder volume increases. This shift in maximum strain suggests that there exists an optimum ratio between the card-side solder volume and the module-side solder volume for the reliability of a given ceramic ball grid array design. The implications of this for the package developers and users are discussed. The calculations indicate that the fatigue life of plastic ball grid arrays is almost insensitive to the card-side solder volume.

Finite element modeling of thermal fatigue and damage of solder joints in a ceramic ball grid array package

A nonlinear finite element model is presented for analyzing the cyclic and thermal fatigue loading and for viscoplastic damage characterization of the lead-tin (Pb-Sn) solder joints in a ceramic ball grid array (CBGA) surface mount package. An approach using a Δ ∈ eq in -modified Coffin-Manson equation is proposed to estimate the fatigue life of the solder joints. The Δ ∈ eq in represents a saturated equivalent inelastic strain range as determined by the finite element model. The present study shows that the predictied fatigue life and the associated damage mechanism of the solder joint agree reasonably well with the test data for the 18,25, and 32 mm CBGA packages run at a cyclic temperature load of 0°C/100°C with a frequency of 1.5 cycles per hour. Analysis also shows that a preferred failure site is expected to occur in and around the Pb37-Sn63 solder attachment of the solder joint. A time-dependent (creep induced) damage mechanism is found to be more pronounced than the time-independent (plastic deformation) mechanism.

The reliability nomograph-graphical predictor of package/module interconnect reliability

Many computer hardware manufacturers can adequately characterize the reliability of today's solder interconnect. However, the procedure is often one requiring a lengthy and complicated accelerated test. The alternative to performing an accelerated test is the use of validated predictive models. These models can be complex requiring specialized analytical skills of the user. An alternate approach is proposed and developed here. One in which the reliability of a package/solder interconnect can be predicted through a series of coupled graphs, i.e., pkg., thermal perf/spl rarr/pkg. structural perf/spl rarr/interconnect reliability. The thermal and structural performance graphs are generated through the use a package/printed wiring board (PWB) finite element model while the interconnect reliability graph uses the Norris-Landsberg model. The coupled figures are known collectively as a nomograph. Nomographs for plastic ball grid array (PBGA), plastic quad flat packs (PQFP), thin small outline packages (TSOP), ceramic ball grid array (CBGA), and ceramic column grid array (CCGA) packages are presented.

Heat transfer and nonlinear thermal stress analysis of a convective surface mount package

Most prior heat transfer and thermal stress analyses of convective surface mount packages have relied on either an isothermal (constant temperature) model or a constant heat transfer coefficient model. This usually leads to a concern for the accurate estimation of the local temperature distributions and the induced stresses. To release this concern, this paper presents the use of the finite element analysis method in predicting the local temperature and stress distributions of a ceramic ball grid array (CBGA) package. The analysis has included a local heat transfer coefficient model with the thermal boundary condition that was obtained from a previous computational fluid dynamics (CFD) solution. The results are compared with that predicted by the isothermal model and the constant heat transfer coefficient model. Instances where the temperature dependent and elastic-plastic material behavior are significant to produce nonlinear stress response in some components of the modeled package are also examined.

Yield learning in integrated circuit package assembly

This paper describes a yield learning model for integrated circuit package assembly. The goal was to provide a management tool for making yield projections, resource allocations, understanding operating practices, and performing what-if analyses. The model was developed using a series of case studies of packages entering manufacturing. These studies were a tape carrier package (TCP) at Intel, Chandler, AZ, a ceramic ball grid array (CBGA) and plastic quad flat pack (PQFP) at IBM, Bromont, P.Q., Canada, and a plastic ball grid array (PBGA) at Motorola, Austin, TX. These packages covered a wide range of technologies, including liquid and overmolded encapsulation, wirebond and controlled collapsed chip connection (C4) chip connections, and tape automated bonding (TAB), ceramic, laminate, and leadframe substrates. The factors that affect yield learning rates (e.g., process complexity, production volumes, personnel experience) were identified and a nonlinear spreadsheet-based response surface model was built. The model separates out the underlying chronic yield from excursions due to human error, equipment failure, etc. The model has been shown to accurately predict the yield ramp as a function of the factor values, One of the conclusions of this work is that all of the very dissimilar assembly processes had very similar factors, with very similar factor sensitivities and rankings in terms of how each affected the yield learning rate. In all cases, the most important factors were operator experience, changes in line volume, types of work teams, process complexity, equipment upgrades, and technology type. Since the yield ramp for a new product will hopefully be short, the model must be calibrated for a particular product very quickly. We have developed a graphical interface and tuning procedure so that when the production data is readily available, the tuning procedure takes only a few days.

Modeling thermally induced viscoplastic deformation and low cycle fatigue of CBGA solder joints in a surface mount package

A nonlinear finite element model was used to analyze the thermally induced viscoplastic deformation and low cycle fatigue behavior of the lead-tin (Pb-Sn) solder joints in a 32 mm ceramic ball grid array (CBGA) surface mount package. The effects of the cyclic frequency, hold (dwell) time, and temperature ramp rate on the response of the viscoplastic (creep and plastic) deformation for the CBGA solder joints were studied by applying four different low cycle thermal fatigue loads to the package. The modeling results show that the maximum viscoplastic strains occur in and around the edge CBGA solder joint. The cyclic creep strain (ratchetting) is very significant and dominates the constituent of the accumulated viscoplastic strain. The equivalent plastic strain increases with the increase of cyclic frequency and ramp rate, and decreases as the hold time increases. However, the equivalent creep strain decreases with the increase of cyclic frequency and ramp rate, but increases as the hold time increases. In the solder joint, the Pb37-Sn63 solder paste has approximately 2/spl times/ larger equivalent plastic strains, and 10/spl times/ larger equivalent creep strains than that in the Pb90-Sn10 solder ball during thermal cycling.

Measurement, modeling, and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multilayer ceramic BGA

This paper presents the simultaneous switching noise (SSN) measurements, modeling, and simulation of a flip-chip complementary metal-oxide-semiconductor (CMOS) application-specific integrated circuit (ASIC) test chip on a multilayer ceramic ball grid array (CBGA) package. Technology and design features of the chip and package test vehicles are described. Time-domain noise measurement techniques and results are presented in detail. Circuit modeling and simulation methodologies are developed and validated by strong correlation between measurement and simulation results.

Improving the Heat Dissipation of Multilayer Ceramic Modules by the Use of CBGA Connections on HTCC and LTCC

By the use of ceramic ball grid array connections, the number of I/Os can be increased substantially in comparison with PGA (pin grid array) while maintaining an unchanged module size. In most cases, this also signifies a higher packing density and thus a higher power density, which must be dissipated as occurring heat. The fact that the dissipation of heat can also be improved considerably by the use of modules with CBGA (ceramic ball grid array) connections instead of PGA connections is demonstrated on a simulation model. Moreover, the use of chip carriers made of different ceramics (LTCC or Al2O3) has a substantial influence on the possible heat dissipation (LTCC= low temperature cofired ceramic).

Effect of PCB finish on the reliability and wettability of ball grid array packages

Organic protective coatings (OPC) and metallic plating chemistries have emerged as alternatives to traditional hot air solder leveling (HASL) to ensure the solderability of printed circuit boards (PCB). This study examined a number of commercially-available printed circuit board finishes to determine their intrinsic solderability and their effect on the solder joint reliability of ball grid array (BGA) packages. The PCB finishes included OPC (Entek Plus CU-106A and MEC-seal), immersion Au over electroless Ni (LeaRonal, MacDermid, Shipley, and Technique), electroless Pd over Ni, electroless Sn over Cu, immersion Bi over Cu, and HASL. Solderability tests were performed by reflowing 20-mil diameter solder spheres on variously aged test coupons and then quantitatively measuring the area and shape of the solder after cooling. The immersion Au finishes generally exhibited excellent wettability as a function of N/sub 2/ reflow aging as compared with the OPCs and HASL. The Pd-Ni, Sn, and one of the Ni-Au finishes exhibited poor wetting when exposed to an 85/spl deg/C/85% RH environment. Solder joint reliability was measured for a 41 I/O ceramic BGA using cyclic thermal shock (nominally -55-125/spl deg/C) and three point bending. All finishes tested behaved similarly in thermal shock. The Au finishes generally performed worse in three-point bending as compared to OPC and HASL. The wetting and reliability results are correlated with the structure and composition of the finishes and the solder joints.

Reliability comparison of two metallurgies for ceramic ball grid array : DONALD R. BANKS, TERRY E. BURNETTE, R. DAVID GERKE, EMPHRAIM MANNO and SHYAM MATTAY. IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B, 18(1), 53 (February 1995)

Reliability comparison of two metallurgies for ceramic ball grid array : DONALD R. BANKS, TERRY E. BURNETTE, R. DAVID GERKE, EMPHRAIM MANNO and SHYAM MATTAY. IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B, 18(1), 53 (February 1995)

A hi-density C4/CBGA interconnect technology for a CMOS microprocessor

The application of a controlled-collapse chip connection (C4), ceramic-ball-grid array (CBGA) single-chip package to the Motorola 88110 RISC CMOS microprocessor is presented. Also presented are the zero-level to second-level interconnection technologies and the various design considerations: from the on-chip redistribution metal to the printed-circuit board definition. In addition to an overview of the interconnect technology, we discuss the: (1) printed-circuit board design, (2) first-level and second-level assembly, (3) electrical modeling and characterization, (4) thermal management, and (5) controlled-collapse chip connection (C4) and ceramic-ball-grid array (CBGA) interconnection reliability and solder-fatigue life estimates. For this study four discipline-specific technology test vehicles were used to evaluate the assembly, electrical, thermal, and reliability aspects of this C4/CBGA interconnect technology. The design and use of each test vehicle is presented. In contrast to a 51 mm, wirebond pin-grid array package (PGA), the C4/CBGA package offers several technological improvements for high-performance RISC microprocessors, which are: (1) a much smaller use of printed-circuit board area, for example, the 361 I/O 25 mm package reduces the original package footprint by approximately 75%, (2) a surface mountable package, (3) the package-to-board assembly is possible with industry-standard surface-mount equipment, (4) the use of C4 and CBGA technology reduce the electrical parasitics, (5) the junction-to-cap thermal resistance was less than 1.5/spl deg/C/W, and (6) the CBGA solder joints are predicted to exceed 3,500 on/off cycles, of 25/spl deg/C to 55/spl deg/C cycling, with a failure rate of 100 parts per million (ppm) per package.

C-4/CBGA comparison with other MLC single chip package alternatives

Future applications, will require higher I/O counts, more densification, lower cost, and greater performance. This paper demonstrates why area-array based chip-to-substrate and substrate-to-card interconnections are strategic, particularly solder bump flip chips (SBFC or C-4) and ceramic ball or column grid arrays (CBGA/CCGA), respectively. That is, SBFC are capable of high pin counts coupled with high yields, performance, and reliability. Moreover, recently introduced CBGA/CCGA interconnections provide substantial benefits over standard pin grid array (PGA) packages. Also, CBGA/CCGA packages possess the highest density achievable at the card level when utilized in conjunction with SBFC-mounted die.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Reliability comparison of two metallurgies for ceramic ball grid array

Surface-mountable ceramic ball grid array (CBGA) packages have proven to be attractive in a variety of applications as designers seek to maximize electrical performance, reduce card real estate, and improve manufacturing process yields. In support of the PowerPC family of microprocessors, 21 mm CBGA packages (256 leads) were used to evaluate two different ball metallurgies-90/10 Pb/Sn and 62/36/2 Sn/Pb/Ag. Test modules were assembled to printed circuit cards and cycled at 0 to 100/spl deg/C and -40 to 125/spl deg/C to evaluate the relative fatigue behavior of the interconnections. Ball attach techniques and module-to-card assembly processes are described, including screening, placement, and reflow. Failure mechanisms and fatigue reliability are discussed for both metallurgies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>