A hi-density C4/CBGA interconnect technology for a CMOS microprocessor

Abstract

The application of a controlled-collapse chip connection (C4), ceramic-ball-grid array (CBGA) single-chip package to the Motorola 88110 RISC CMOS microprocessor is presented. Also presented are the zero-level to second-level interconnection technologies and the various design considerations: from the on-chip redistribution metal to the printed-circuit board definition. In addition to an overview of the interconnect technology, we discuss the: (1) printed-circuit board design, (2) first-level and second-level assembly, (3) electrical modeling and characterization, (4) thermal management, and (5) controlled-collapse chip connection (C4) and ceramic-ball-grid array (CBGA) interconnection reliability and solder-fatigue life estimates. For this study four discipline-specific technology test vehicles were used to evaluate the assembly, electrical, thermal, and reliability aspects of this C4/CBGA interconnect technology. The design and use of each test vehicle is presented. In contrast to a 51 mm, wirebond pin-grid array package (PGA), the C4/CBGA package offers several technological improvements for high-performance RISC microprocessors, which are: (1) a much smaller use of printed-circuit board area, for example, the 361 I/O 25 mm package reduces the original package footprint by approximately 75%, (2) a surface mountable package, (3) the package-to-board assembly is possible with industry-standard surface-mount equipment, (4) the use of C4 and CBGA technology reduce the electrical parasitics, (5) the junction-to-cap thermal resistance was less than 1.5/spl deg/C/W, and (6) the CBGA solder joints are predicted to exceed 3,500 on/off cycles, of 25/spl deg/C to 55/spl deg/C cycling, with a failure rate of 100 parts per million (ppm) per package.