Processor Frequency Research Articles

Virtual Batching: Request Batching for Server Energy Conservation in Virtualized Data Centers

Many power management strategies have been proposed for enterprise servers based on dynamic voltage and frequency scaling (DVFS), but those solutions cannot further reduce the energy consumption of a server when the server processor is already at the lowest DVFS level and the server utilization is still low (e.g., 10 percent or lower). To achieve improved energy efficiency, request batching can be conducted to group received requests into batches and put the processor into sleep between the batches. However, it is challenging to perform request batching on a virtualized server because different virtual machines on the same server may have different workload intensities. Hence, putting the shared processor into sleep may severely impact the application performance of all the virtual machines. This paper proposes Virtual Batching, a novel request batching solution for virtualized servers with primarily light workloads. Our solution dynamically allocates CPU resources such that all the virtual machines can have approximately the same performance level relative to their allowed peak values. Based on this uniform level, Virtual Batching determines the time length for periodically batching incoming requests and putting the processor into sleep. When the workload intensity changes from light to moderate, request batching is automatically switched to DVFS to increase processor frequency for performance guarantees. Virtual Batching is also extended to integrate with server consolidation for maximized energy conservation with performance guarantees for virtualized data centers. Empirical results based on a hardware testbed and real trace files show that Virtual Batching can achieve the desired performance with more energy conservation than several well-designed baselines, e.g., 63 percent more, on average, than a solution based on DVFS only.

HAPPE: Human and Application-Driven Frequency Scaling for Processor Power Efficiency

Conventional dynamic voltage and frequency scaling techniques use high CPU utilization as a predictor for user dissatisfaction, to which they react by increasing CPU frequency. In this paper, we demonstrate that for many interactive applications, perceived performance is highly dependent upon the particular user and application, and is not linearly related to CPU utilization. This observation reveals an opportunity for reducing power consumption. We propose Human and Application driven frequency scaling for Processor Power Efficiency (HAPPE), an adaptive user-and-application-aware dynamic CPU frequency scaling technique. HAPPE continuously adapts processor frequency and voltage to the learned performance requirement of the current user and application. Adaptation to user requirements is quick and requires minimal effort from the user (typically a handful of key strokes). Once the system has adapted to the user's performance requirements, the user is not required to provide continued feedback but is permitted to provide additional feedback to adjust the control policy to changes in preferences. HAPPE was implemented on a Linux-based laptop and evaluated in 22 hours of controlled user studies. Compared to the default Linux CPU frequency controller, HAPPE reduces the measured system-wide power consumption of CPU-intensive interactive applications by 25 percent on average while maintaining user satisfaction.

Wireless Image Transmission System

A wireless image transmission system is proposed, which in order to offset the disadvantages of wire video monitor laying points hard, and disadvantages of wire video monitor implementing hard in bad circumstance. The core of the system is TI series of C5000 high speed DSP processor and radio frequency wireless communication chip. Through DSP transplantation of JPEG compression algorithm, complete image collection and image compression through DSP, use wireless receiving and sending module to complete wireless images data transmission. Use wireless receiving and sending module instead of emitter and network as image data transmission device, low cost, not required network fee, system can real-time complete terminal images collection and show. It can apply community guard and video monitor of deploying points urgently in the electric power system, factory, bank and other important department, which dont require higher performance.

Effect of Compensation and Arbitrary Sampling in interpolators for Different Wireless Standards on FPGA Platform

In any communication system, it is desired to convert very high sampling frequency to processor frequency. This can be implemented by using efficient use of Multirate Filters. In this paper, the Multi rate filters have been implemented very effectively on FPGA Platform. Also, it has been shown that how performance of Multi rate filters can be improved using different techniques at different sampling rates. The filter structures suggested here have wide applications in the field of ADC (Analog to Digital Converter), DUC (Digital Up Converter)/DDC(Digital Down Converter) and in almost every stage of communication system wherever convolution is being done. The results also show that proposed multi rate filter structures can be used very effectively and efficiently in designing and development of very large scale integration of Digital communication system.

Use of compiler optimization of software bypassing as a method to improve energy efficiency of exposed data path architectures

In the design of embedded systems, hardware and software need to be co-explored together to meet targets of performance and energy. With the use of application-specific instruction-set processors, as a stand-alone solution or as a part of a system on chip, the customization of processors for a particular application is a known method to reduce energy requirements and provide performance. In particular, processor designs with exposed data paths trade compile time complexity for simplified control hardware and lower running costs. An exposed data path also allows the removal of unused components of interconnection network, once the application is compiled. In this paper, we propose the use of a compiler technique for processors with exposed data paths, called software bypassing. Software bypassing allows the compiler to schedule data transfers between execution units directly, bypassing the use of a general-purpose register file, increasing scheduling freedom, with reduced dependencies induced by the reuse of registers, decreasing the number of read and write accesses to register files, and allowing the use of register files with less read and write ports while maintaining or improving performance and maintaining reprogrammability. We compare our proposal against an architecture exploration technique, connectivity reduction, which finds in compiled application all interconnection network components that are used and removes those which are not, leading to an energy-efficient application-specific instruction-set processor. We observe that the use of software bypassing leads to improvements in application speed, with architectures having the smallest number of register file ports consistently outperforming architectures with larger number of ports, and reduction in energy consumption. In contrast, connectivity reduction maintains the same application speed, reduces energy consumption, and allows for increase in processor frequency; however, with the clock frequency increased to match the performance of software bypassing, energy consumption grows. We also observe that in case reprogrammability is not an issue, the most energy-efficient solution is a combination of software bypassing and connectivity reduction.

SyRaFa: Synchronous Rate and Frequency Adjustment for Utilization Control in Distributed Real-Time Embedded Systems

To efficiently utilize the computing resources and provide good quality of service (QoS) to the end-to-end tasks in the distributed real-time systems, we can enforce the utilization bounds on multiple processors. The utilization control is challenging especially when the workload in the system is unpredictable. To handle the workload uncertainties, current research favors feedback control techniques, and recent work combines the task rate adaptation and processor frequency scaling in an asynchronous way for CPU utilization control, where task rates and the processor frequencies are tuned asynchronously in two decoupled control loops for control convenience. Since the two manipulated variables, task rates and processor frequencies, contribute to the CPU utilizations together with strong coupling, adjusting them asynchronously may degrade the utilization control performance. In this paper, we provide a novel scheme to make synchronous rate and frequency adjustment to enforce the utilization setpoint, referred to as SyRaFa scheme. SyRaFa can handle the workload uncertainties by identifying the system model online and can simultaneously adjust the manipulated variables by solving an optimization problem in each sampling period. Extensive evaluation results demonstrate SyRaFa outperforms the existing schemes especially under severe workload uncertainties.

The need for speed and stability in data center power capping

Data centers can lower costs significantly by provisioning expensive electrical equipment (such as UPS, diesel generators, and cooling capacity) for the actual peak power consumption rather than server nameplate power ratings. However, it is possible that this under-provisioned power level is exceeded due to software behaviors on rare occasions and could cause the entire data center infrastructure to breach the safety limits. A mechanism to cap servers to stay within the provisioned budget is needed, and processor frequency scaling based power capping methods are readily available for this purpose. We show that existing methods, when applied across a large number of servers, are not fast enough to operate correctly under rapid power dynamics observed in data centers. We also show that existing methods when applied to an open system (where demand is independent of service rate) can cause cascading failures in the software service hosted, causing the service performance to fall uncontrollably even when power capping is applied for only a small reduction in power consumption. We discuss the causes for both these short-comings and point out techniques that can yield a safe, fast, and stable power capping solution. Our techniques use admission control to limit power consumption and ensure stability, resulting in orders of magnitude improvement in performance. We also discuss why admission control cannot replace existing power capping methods but must be combined with them.

CPPM: a Comprehensive Power-aware Processor Manager for a Multicore System

The growing functionality of mobile devices explains increasing system performance requirements and the subsequent wide adoption of multicore processors. As mobile systems are battery powered, battery life largely limits these high performing multicore mobile devices. Developing an efficient power-aware processor manager for mobile multicore systems has received considerable atten- tion. The conventional processor management system of embedded systems e.g., the Linux kernel scheduler incorporates an automatic scheme to control peripheral operations and processor frequency. However, this mechanism fails to consider user requirements, task loading, and operating status of processors in the multicore system to satisfy operating requirements. Therefore, this work presents a novel power-aware multicore processor manager, referred to herein as a comprehensive power-aware processor manager (CPPM), which integrates a system configuration selection algorithm (BPM-DFS), task re-scheduling mechanism (CTM), and precise system power estimation mechanism (PPM). The CPPM manager can dynamically set system configurations and rearrange executed tasks among multiple cores to comply with the limitation of power consumption that is assigned by the user. Moreover, the proposed CPPM is implemented on quad-core x86 Android system to compare with the capabilities of other scheduling mechanisms.

High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms

The potential computational power of today multicore processors has drastically improved compared to the single processor architecture. Since the trend of increasing the processor frequency is almost over, the competition for increased performance has moved on the number of cores. Consequently, the fundamental feature of system designs and their associated design flows and tools need to change, so that, to support the scalable parallelism and the design portability. The same feature can be exploited to design reconfigurable hardware, such as FPGAs, which leads to rethink the mapping of sequential algorithms to HDL. The sequential programming paradigm, widely used for programming single processor systems, does not naturally provide explicit or implicit forms of scalable parallelism. Conversely, dataflow programming is an approach that naturally provides parallelism and the potential to unify SW and HDL designs on heterogeneous platforms. This study describes a dataflow-based design methodology aiming at a unified co-design and co-synthesis of heterogeneous systems. Experimental results on the implementation of a JPEG codec and a MPEG 4 SP decoder on heterogeneous platforms demonstrate the flexibility and capabilities of this design approach.

A concurrent van Emde Boas array as a fast and simple concurrent dynamic set alternative

SUMMARYIncreasing demand for computationally efficient algorithms and processors has turned the attention of researchers toward parallel and concurrent solutions. Because the frequency of contemporary processors cannot be tweaked infinitely, the only hopes for squeezing more performance from computers are parallel processing and parallel computation. The important part of every parallel solution is concurrent data structures, which allow multithread programming environments to be taken advantage of. In this article, a new concurrent dynamic set structure is proposed. It is based on the van Emde Boas trees concept, where on every node of a tree, an array of the node's children is stored. The structure is equipped with a simple but effective locking algorithm, which allows it to be used concurrently by any number of threads. The presented algorithm idea is accompanied by an experimental implementation written in JAVA 6. Preliminary tests prove that, especially for moderately larger data sets with a predominance of read operations, the concurrent van Emde Boas array proposed in this article may be a viable alternative for other structures providing a similar functionality. Copyright © 2013 John Wiley & Sons, Ltd.

A Low Power Multimedia Processor Implementing Dynamic Voltage and Frequency Scaling Technique and Fast Motion Estimation Algorithm Called “Adaptively Assigned Breaking-Off Condition (A<sup>2</sup>BC)”

A Low Power Multimedia Processor Implementing Dynamic Voltage and Frequency Scaling Technique and Fast Motion Estimation Algorithm Called “Adaptively Assigned Breaking-Off Condition (A<sup>2</sup>BC)”

A Study on the System of Radio Frequency Identification and Localization Works in UHF

This paper designs a hand-held radio frequency identification and localization terminal based on ARM Cortex-M3 processor and active radio frequency tags based on 8051 processor. This terminal uses STM32F103VET6 as its master controller, these tags use STC12C2052AD as their master controller. They all use Nordic nRF905 as their radio frequency identification module. The system works in 433M/868M/915MHz ISM UHF band and can read, write and locate radio frequency tags within 50m indoors. The actual measurement of active radio frequency tags shows that this terminal is highly stable and comparable in 433M/868M/915M ultra-high frequency radio identification and localization. The test results of this system are also analyzed and presented.

Energy efficient communications in quantum chemistry applications

Modern supercomputing platform designers are becoming increasingly aware of the operational costs and reliability issues, which are rising due to high power consumption of such systems. At the same time, high-performance application developers are taking pro-active steps towards less energy consumption without a significant performance loss. One way to accomplish energy savings during application execution is to change the processor frequency dynamically when processor is not busy, such as during certain communication stages. Previously, the authors have proposed a runtime procedure that identifies communication phases in parallel applications to apply frequency scaling efficiently and without much overhead. The present work applies the phase detection procedure to parallel electronic structure calculations, performed by a widely used package GAMESS. High computational intensity of these calculations and the GAMESS communication model, which distinguishes computation and communication processes, motivated the investigations in this paper. They have led to several insights as to the role of process-core mapping in the application of dynamic frequency scaling during communications.

Three-phase time-aware energy minimization with DVFS and unrolling for Chip Multiprocessors

Energy consumption has been one of the most critical issues in the Chip Multiprocessor (CMP). Using the Dynamic Voltage and Frequency Scaling (DVFS), a CMP system can achieve a balance between the performance and the energy-efficiency. In this paper, we propose a three-phase discrete DVFS algorithm for a CMP system dedicated to applications where the period of the applications’ task graph is smaller than the deadline of tasks. In these applications, multiple task graphs are unrolled and then concatenated together to form a new task graph. The proposed DVFS algorithm is applied to the newly formed task graph to stretch tasks’ execution time, lower operating frequencies of processors and achieve the system power efficiency. Experimental results show that the proposed algorithm reduces the energy dissipation by 25% on average, compared to previous DVFS approaches.

Effects of Lower Frequency-to-Electrode Allocations on Speech and Pitch Perception with the Hybrid Short-Electrode Cochlear Implant

Because some users of a Hybrid short-electrode cochlear implant (CI) lose their low-frequency residual hearing after receiving the CI, we tested whether increasing the CI speech processor frequency allocation range to include lower frequencies improves speech perception in these individuals. A secondary goal was to see if pitch perception changed after experience with the new CI frequency allocation. Three subjects who had lost all residual hearing in the implanted ear were recruited to use an experimental CI frequency allocation with a lower frequency cutoff than their current clinical frequency allocation. Speech and pitch perception results were collected at multiple time points throughout the study. In general, subjects showed little or no improvement for speech recognition with the experimental allocation when the CI was worn with a hearing aid in the contralateral ear. However, all 3 subjects showed changes in pitch perception that followed the changes in frequency allocations over time, consistent with previous studies showing that pitch perception changes upon provision of a CI.

TCEC: Temperature and Energy-Constrained Scheduling in Real-Time Multitasking Systems

The ongoing scaling of semiconductor technology is causing severe increase of on-chip power density and temperature in microprocessors. This urgently requires both power and thermal management during system design. In this paper, we propose a model checking-based technique using extended timed automata to solve the processor frequency assignment problem in a temperature and energy-constrained multitasking system. We also develop a polynomial time-approximation algorithm to address the state-space explosion problem caused by symbolic model checker. Our approximation scheme is guaranteed to not generate any false-positive answer, while it may return false-negative answer in rare cases. Our method is universally applicable since it is independent of any system and task characteristics. Experimental results demonstrate the usefulness of our approach.

Accurate energy characterization of OS services in embedded systems

As technology scales for increased circuit density and performance, the management of power consumption in embedded systems is becoming critical. Because the operating system (OS) is a basic component of the embedded system, the reduction and characterization of its energy consumption is a main challenge for the designers. In this work, a flow of low power OS energy characterization is introduced. The variation of the energy and power consumption of the embedded OS services is studied. The remainder of this article details the methods used to determine energy and power overheads of a set of basic services of the embedded OS: scheduling, context switch and inter-process communication. The impacts of hardware and software parameters like processor frequency and scheduling policy on the energy consumption are analyzed. Also, models and laws of the power and energy are extracted. Then, to quantify the low power OS energetic overhead, the obtained models are integrated in the system level design. Our method allows estimating the energy consumption of the low power OS services when running an application on a specific hardware platform.

Extended scheduler for efficient frequency scaling in virtualized systems

Nowadays, virtualization is present in almost all computing infrastructures. Thanks to server consolidation and VM migration, virtualization helps in power reduction. However, modern powerful computers with higher processor frequency, multiple cores and multiple CPUs constitute the main factor contributing to the continuous increase of energy consumption. In this context, energy management takes a critical importance. A hardware technology, called Dynamic Voltage and Frequency Scaling (DVFS), serves to dynamically modify the processor frequency (according to the CPU needs) in order to achieve less energy consumption. However, lowering frequency also generates poor virtual machine (VM) performance. In this paper, we propose a solution consisting of an extended VM scheduler and DVFS, and report some experiments based on this proposal. This enhanced scheduler, according to VM CPU load, dynamically scales processor frequency in order to save energy. The idea is to adapt the current VM scheduler to analyze CPU load, and modify the current processor frequency to the lowest possible, but still support the guaranteed VM performance. The algorithm is designed and simulated on a web server as the sample application and Xen as the virtualization platform. Test results and performance evaluations prove our design and implementation.

Energy-aware dynamic slack allocation for real-time multitasking systems

Dynamic voltage scaling (DVS) has been a very effective technique for processor energy reduction. It adjusts processor voltage and frequency level during runtime. In this article, we propose a general and flexible processor voltage scaling algorithm for real-time multitasking systems. Our approach focuses on exploiting dynamic slack that is created when a task finishes earlier than its estimated worst-case execution time (WCET). Our algorithm is efficient enough to execute at runtime and can be configured flexibly to make tradeoffs between running time and energy savings. By rescheduling tasks effectively, we can achieve almost as much energy savings as if there is no arrival time constraints. Furthermore, our approach can effectively incorporate both leakage power consumption as well as variable scaling overhead. Also, it is relatively independent of task characteristics and scheduling policy. Experimental results show that our technique can achieve significant energy savings at runtime over statically generated schedules and up to 12% more savings compared to the state-of-art techniques.

Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches

Cache memories dissipate an important amount of the energy budget in current microprocessors. This is mainly due to cache cells are typically implemented with six transistors. To tackle this design concern, recent research has focused on the proposal of new cache cells. An <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -bit cache cell, namely macrocell, has been proposed in a previous work. This cell combines SRAM and eDRAM technologies with the aim of reducing energy consumption while maintaining the performance. The capacitance of eDRAM cells impacts on energy consumption and performance since these cells lose their state once the retention time expires. On such a case, data must be fetched from a lower level of the memory hierarchy, so negatively impacting on performance and energy consumption. As opposite, if the capacitance is too high, energy would be wasted without bringing performance benefits. This paper identifies the optimal capacitance for a given processor frequency. To this end, the tradeoff between performance and energy consumption of a macrocell-based cache has been evaluated varying the capacitance and frequency. Experimental results show that, compared to a conventional cache, performance losses are lower than 2% and energy savings are up to 55% for a cache with 10 fF capacitors and frequencies higher than 1 GHz. In addition, using trench capacitors, a 4-bit macrocell reduces by 29% the area of four conventional SRAM cells.