Effect of Compensation and Arbitrary Sampling in interpolators for Different Wireless Standards on FPGA Platform

Rajeev Ratan,Dr.Sanjay Sharma,Dr Amit K Kohli

doi:10.19026/rjaset.6.4171

Abstract

In any communication system, it is desired to convert very high sampling frequency to processor frequency. This can be implemented by using efficient use of Multirate Filters. In this paper, the Multi rate filters have been implemented very effectively on FPGA Platform. Also, it has been shown that how performance of Multi rate filters can be improved using different techniques at different sampling rates. The filter structures suggested here have wide applications in the field of ADC (Analog to Digital Converter), DUC (Digital Up Converter)/DDC(Digital Down Converter) and in almost every stage of communication system wherever convolution is being done. The results also show that proposed multi rate filter structures can be used very effectively and efficiently in designing and development of very large scale integration of Digital communication system.

Highlights

The digital filters have emerged as a strong option for removing noise, shaping spectrum, and minimizing inter-symbol interference in communication architectures
Sample Rate Conversions ensures the effective implementation of Digital Up/Down Convertors for Though the implementation of Signal Processing systems on applicationspecific integrated circuit (ASIC) provide better optimized devices, but the cost of such devices are rising
With the recent advances in Field-Programmable gate Array (FPGA) technology, the more complex devices providing highspeed as required in DSP applications are available. .the FPGA has advantage of reconfiguration which provides an upper hand over ASIC devices

Summary

INTRODUCTION

The digital filters have emerged as a strong option for removing noise, shaping spectrum, and minimizing inter-symbol interference in communication architectures. The Farrow filters have been implemented for fractional delay and arbitrary change in sample rate conversion on FPGA platform which is the need of any modern digital communication system. Both of these filters gives a better performance than the common filter structures in terms of speed of operation, cost and power consumption in real-time. In the two-stage solutions of Fig. 5 and 6, the role of CIC decimator (interpolator) is to convert the sampling rate by the large conversion factor N, whereas the FIR filter T (z) provides the desired transition band of the overall decimator (interpolator) and compensates the pass-band characteristic of the CIC filter (Crochiere and Rabiner, 1983; Ricardo, 2008; Vesma, 1999; Farrow, 1988). Multistage FIR filter (Abu-Al-Saud and Stuber, 2003; Hentschel and Fettweis, 2000b)

MATERIALS AND METHODS

RESULTS AND DISCUSSION

CONCLUSION