IF Waveform Generation and Digital Down Converter with RTIO Board

Abstract

In RADAR systems, a signal is transmitted, it bounces off an object and it is later received by some type of receiver. Once the RADAR receives the returned signal, it calculates useful information. Any received signals from the receiver must be pre-processed before sending it to the signal Processing stages, DDC helps in front-end processing or pre-processing the received signal before transferring the data to signal processing units. A fundamental part of many communications systems is Digital Down Conversion (DDC). To optimize the conventional DDC (Single stage FIR filter) with respect to hardware Complexity, Speed, Power dissipation, Multi stage FIR filter approach is used which is more efficient. The aim of the project is to implement Digital Down Converter (DDC) on Virtex-5 FPGA device efficiently. The received IF signal is down converted to base band level using DDC. The technique greatly reduces the amount of effort required for subsequent processing of the signal without loss of any of the information carried. DDCs implemented on FPGA have more flexible frequency and phase characteristics and higher precision computation.DDC will be implemented with above advantages on Xilinx FPGA Virtex-5. Results are analyzed using ModelSim, ChipScope Pro Analyzer and MATLAB simulation.