Abstract
Modern supercomputing platform designers are becoming increasingly aware of the operational costs and reliability issues, which are rising due to high power consumption of such systems. At the same time, high-performance application developers are taking pro-active steps towards less energy consumption without a significant performance loss. One way to accomplish energy savings during application execution is to change the processor frequency dynamically when processor is not busy, such as during certain communication stages. Previously, the authors have proposed a runtime procedure that identifies communication phases in parallel applications to apply frequency scaling efficiently and without much overhead. The present work applies the phase detection procedure to parallel electronic structure calculations, performed by a widely used package GAMESS. High computational intensity of these calculations and the GAMESS communication model, which distinguishes computation and communication processes, motivated the investigations in this paper. They have led to several insights as to the role of process-core mapping in the application of dynamic frequency scaling during communications.
Published Version
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