Cell Array Structure Research Articles

Establishment of a cascaded microfluidic single cell analysis system for molecular and functional heterogeneity analysis of circulating tumor cells

Single cell heterogeneity analysis of circulating tumor cells (CTCs) is expected to reveal important tumor biological information for the evaluation and prediction of tumor stage and metastatic progression. Although various methods have been proposed to isolate and detect CTCs, consecutive CTCs sorting and in-situ multi-dimensional heterogeneity analysis in a cascaded system remain challenging. Here, a cascaded microfluidic chip was constructed, successively integrating a spiral structure for size-based removal of blood cells and a single cell array structure for the subsequent capture of CTCs, complementing the advantages of high throughput and high separation purity for both structures. Importantly, the molecular and functional heterogeneity analysis of CTCs can be in-situ realized and real-time observed at the single-cell level. Using this system, we captured CTCs and situ-analyzed the heterogeneity of single CTCs from different types of cancer patients, finding that mesenchymal phenotype is present in more CTCs at the advanced stage, and CTCs show active motility and division ability in metastatic patients. Therefore, the cascaded microfluidic chip offers an effective strategy for studying the molecular and functional heterogeneity of single CTCs, providing critical information for the evaluation of tumor progression and metastasis.

Single Event Effects in 3-D NAND Flash Memory Cells With Replacement Gate Technology

We studied the heavy-ion single event effect response of 3D NAND Flash memory cells with charge-trap based replacement gate technology. Error cross sections, threshold voltage shifts, and underlying mechanisms are discussed. The behavior of replacement gate cells is compared with previous generations of Flash NAND memory cells with floating gate architecture, both planar and 3D. The cell array structure, the technology parameters, and the materials impacting on radiation susceptibility of the different types of cells are discussed.

A Negative Index Nonagonal CSRR Metamaterial-Based Compact Flexible Planar Monopole Antenna for Ultrawideband Applications Using Viscose-Wool Felt.

In this paper, a compact textile ultrawideband (UWB) planar monopole antenna loaded with a metamaterial unit cell array (MTMUCA) structure with epsilon-negative (ENG) and near-zero refractive index (NZRI) properties is proposed. The proposed MTMUCA was constructed based on a combination of a rectangular- and a nonagonal-shaped unit cell. The size of the antenna was 0.825 λ0 × 0.75 λ0 × 0.075 λ0, whereas each MTMUCA was sized at 0.312 λ0 × 0.312 λ0, with respect to a free space wavelength of 7.5 GHz. The antenna was fabricated using viscose-wool felt due to its strong metal–polymer adhesion. A naturally available polymer, wool, and a human-made polymer, viscose, that was derived from regenerated cellulose fiber were used in the manufacturing of the adopted viscose-wool felt. The MTMUCA exhibits the characteristics of ENG, with a bandwidth (BW) of 11.68 GHz and an NZRI BW of 8.5 GHz. The MTMUCA was incorporated on the planar monopole to behave as a shunt LC resonator, and its working principles were described using an equivalent circuit. The results indicate a 10 dB impedance fractional bandwidth of 142% (from 2.55 to 15 GHz) in simulations, and 138.84% (from 2.63 to 14.57 GHz) in measurements obtained by the textile UWB antenna. A peak realized gain of 4.84 dBi and 4.4 dBi was achieved in simulations and measurements, respectively. A satisfactory agreement between simulations and experiments was achieved, indicating the potential of the proposed negative index metamaterial-based antenna for microwave applications.

Research and design of L-type array detector

For the status quo of traveling wave detector array which can synthesize output power but cant improve work bandwidth, this paper proposes a new L-type array detector. Using a capacitance, a photodiode, and two inductance in series to form a single array unit, the L-type array detector has a cascade cell array structure. The results show that L-type detector can carry on power synthesis of the RF output signal, increase working bandwidth to 67 GHz at the same time; Compared with the traditional photoelectric detector, the work bandwidth is tripled. The reasoning method proposed in this paper can be adopted to flexible design of ideal photodiodes, providing a theoretical foundation for future study of photoelectric detectors.

Morphology evolution of self-organized porous structures in silicon surface

Abstract We have investigated the morphology evolution of silicon surface by laser irradiation. A pulsed ns-laser interaction with silicon in aqueous medium can produce self-organized microporous concave cell array structure without any chemicals and auxiliary equipment. Low radiant power was applied to the photo-induced non-thermal silicon surface modification. At the early stage, hemispherical patterns of 2 ∼ 3 µm were formed, maintaining a constant distance from each other without merging. Due to the thermal properties of water, subsurface heating proceeds under the silicon surface. The molten surface leads to the surface modulation to form subsided areas or expansions by nucleation and coalescence, resulting in the formation of a concave cone-shaped porous surface with a diameter of 10 ∼ 20 µm. The AFM reveals that the hierarchical hemispherical structures of two different scales are progressing simultaneously from the early stage.

Aging Management Using a Reconfigurable Switch Network for Arrays of Nonideal Power Cells

Power cells, such as battery cells, solar cells, and fuel cells, are often connected in series and parallel to satisfy a desired amount of power and energy density as well as the terminal voltage. However, it is allowed to compose an array of power cells only when the individual cell has the identical characteristics among each other. However, even originally identical cells eventually have different characteristics due to uneven aging as well as manufacturing process variations. Mixture use of nonidentical cells in the same array results in: 1) significant inefficiency of the whole array; 2) accelerated aging of the weak cells; and 3) degrading healthy cells due to overloading. This paper is first to introduce a system-level solution for cell aging management. The proposed method is dynamic reconfiguration to modify cell grouping and array structures to enable independent control of aged cells from healthy cells. The reconfiguration switch network regroups cells into healthy, aged, and residual array groups, regardless of the physical locations of the aged cells. The proposed network is highly scalable in that the number of switches grows linearly as the number of cells increases. We show practicality of the proposed reconfiguration switch network with a case study of a solid oxide fuel cell (SOFC) system. However, the proposed reconfiguration switch network can be applied to any power cell arrays with an aging effect. We demonstrate significant improvement on the operating hours of an SOFC array. Such improvement is comparable with cell-level independent aging control where every SOFC stack has its own dc–ac inverter.

A novel embryonics electronic cell array structure based on functional decomposition and circular removal self-repair mechanism

Along with the continuous development of aviation detection and deep sea exploration technology, electronic equipment will face with increasingly complicated and harsh natural environment. Traditio...

Three‐dimensional AND flash memory

High-density and high-speed charge-trapping AND flash memory array is fabricated for the first time. A reliability of 104 endurance cycles and uniform program/erase characteristics along with a threshold voltage window >3 V is obtained. The AND array has several advantages, such as high read current drivability regardless of the number of word-lines, immunity to back-pattern dependency, and fast bit-sensing speed based on a parallel connected cell array structure, which are highly appropriate for three-dimensional (3D) stacking. Finally, a novel 3D stacked vertical-AND array is proposed to surpass the limitations of the conventional 3D NAND flash memories.

Array Operation Mode Characterization of Select Gate Lateral Coupling Single-Poly Embedded Nonvolatile Memory

This paper clarifies the reason for the specific array structure and operation methods of a select gate lateral coupling (SGLC) cell array as well as its disturbance immunity. An SGLC cell is a type of single-poly embedded nonvolatile memory that does not require any additional masks and process steps for fabrication. It shows excellent features, such as high programming speed, small cell size comparable to that of SRAM, multitime programmable, and over-erase free characteristic. However, the reasons of its operation methods and cycling limitation have not yet been clarified. We investigated the cycling effect of two types of array structures based on the unit-cell operation method. In particular, in the forward read mode, because of drain-induced barrier lowering (DIBL) that is enhanced by trapped holes at the liner nitride, $V_{T}$ of a programmed cell significantly decreased with a relatively small number of program/erase (P/E) cycles, resulting in a narrower $V_{T}$ window. By adopting the reverse read mode with source-side programming, DIBL enhancement was suppressed and a stable $V_{T}$ window was maintained during P/E cycling. Furthermore, by measuring each disturb method that works with the SGLC cell array structure and the reverse read operation mode, we confirmed that an array size larger than 128-kB sectors is possible.

Structural Solution to Enhance the Sensitivity of a Self-Powered Pressure Sensor for an Artificial Tactile System.

Structural design factors of sensor units have been studied in order to enhance the sensitivity of pressure sensors based on utilizing a piezoelectric material for an artificial tactile sensor. In this study, we have primarily demonstrated the effect of a square pattern array design in a pressure sensor using ZnO nanowires. Nanowires grown on the edge of cells can be bent easily because of growth direction, density control, and buckling effect. Since smaller square pattern arrays induce a higher circumference to cell area ratio, if one sensor unit consists of many micro-level square pattern arrays, the design enhances the piezoelectric efficiency and the sensitivity. As a result, 20 μ m×20 μ m cell arrays showed three times higher pressure sensitivity than 250 μ m×250 μ m cell array structures at a pressure range from 4 kPa to 14 kPa. The induced piezoelectric voltage with the same pressure level also increased drastically. Therefore, the square pattern array design is more appropriate for a high-sensitive pressure sensor than a simple one-body cell design for tactile systems, and it has the advantage of better power efficiency, which is also important for artificial tactile systems. This suggested cell array design can be applied to various systems using piezoelectric nanowires.

Nonvolatile field-programmable gate array using 2-transistor–1-MTJ-cell-based multi-context array for power and area efficient dynamically reconfigurable logic

A dynamically reconfigurable nonvolatile field-programmable gate array (FPGA) with a multi-context (MC) cell array structure that uses three-terminal magnetic tunnel junction (MTJ) devices is proposed. The use of single-ended circuitry together with a 2-transistor and 1-MTJ (2T–1MTJ) context cell allows for the minimization of the area overhead of the context array with nonvolatile storage capability. As the 2T–1MTJ cell has no power line, the leakage current overhead is also minimized. With the proposed implementation, the transistor counts and leakage power during power-on are reduced by 59 and 71%, respectively, compared to the static random-access memory (SRAM)-based implementation using 40-nm CMOS technology.

Control Plug Lateral Coupling Memory Cell Utilizing Uniform Channel Fowler–Nordheim Operation

In this letter, we propose a control-plug (CP) structure logic nonvolatile memory (LNVM) fabricated by a standard logic CMOS process for mobile applications with low-power-consumption requirement. The operating concept of this cell is based on the use of a lateral capacitance coupling between a bar-type CP and a floating gate. Owing to the unique bar-type CP-coupling method and CP-sharing cell array structure, the novel cell has a coupling ratio of over 94% with the lowest fill factor of 344 as a Fowler-Nordheim (FN)-operated LNVM. Furthermore, because of the high coupling ratio and divided-bias operating method, this cell utilizes a uniform-channel FN tunneling program and erase method using a 3.3 V logic peripheral overdrive tolerable voltage of 5.5 V.

An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput

An 8-Mb multi-layered cross-point resistive RAM (ReRAM) macro has been developed with 443 MB/s write throughput (64-bits parallel write per 17.2-ns cycle), which is almost twice as fast as competing methods. It uses the fast switching performance of TaOx ReRAM and a new write architecture to reduce the sneak current in a cross-point cell array structure based on an 0.18-μm process. First, a bidirectional diode as a memory cell select element is developed to reduce the sneak current. Second, PMOS and NMOS are used select transistors in the source follower to realize stable switching for the selected cell in the multi-layered cross-point structure. Third, a hierarchical bitline (BL) structure is employed with a short bitline. Fourth, multi-bit write architecture is developed to realize fast write operation and to suppress the sneak current.

Data retention under gate stress on a NVM array

This work is devoted to an original experimental method based on a classical data retention performed under a continuous gate stress. The method proposed here allows to discriminate the possible leakage paths in a non-volatile electrical memory array, but it is also the first step to the research of an equivalence between electrical stress and thermal stress. A specific array called Cell Array Structure Test (CAST) is used as a fast statistical characterization tool. The measurements are treated by a fast calculation method, allowing to extract the number of marginal cells. One of the major result of this study, apart from demonstrating the relevance of our experimental tool, lies in the demonstration and the confirmation that the charges leakage occurs mainly through tunnel oxide. This method has been applied on an EEPROM CAST – 0.09μm technology node, but it is extendable to a lot of devices and architectures.

An evaluation of the extrinsic cells number in a memory array using cross-correlation products and deconvolution: an instance of a microelectronics experimental inverse problem

This work is devoted to a new, fast and efficient method of evaluating the number of marginal cells in a non-volatile electrical memory array. This extraction from experimental data is fundamentally an inverse problem. The method proposed here is based on simple cross-correlation functions and de-convoluting operations. With the microelectronics device dimension downscaling, the reliability of non-volatile electrical memory has become crucial and any marginal cell can compromise the functioning of the whole array (containing hundreds of thousands of elementary cells). A specific array called Cell Array Structure Test (CAST) has been developed as a useful characterization tool to statistically study retention and endurance performance with few experimental operations. However, this device cannot easily count the low number of failed cells among hundreds of thousands. That is why we had to develop a mathematical method to extract this major quantity from measurements. This method has been validated on an EEPROM CAST – 0.13 µm technology node, but it is extendable to all memory devices integrated in parallel array and more generally to any electrical measurement done in a similar configuration.

Design Technology of stacked NAND type 1-transistor FeRAM

Design technology of stacked NAND type 1-transistor FeRAM has been described. With 39nm design rule feasibility study of 1Tbit memory focused on cell array structure and core circuit has been investigated. 64 layer 8k×8k stacked SGT memory cell array structure and the double ended row and column decoder with SGT have been newly introduced.From the estimation of wordline and bitline delay time this structure enables to reduce the delay time of core circuit to 5ns. Stacked NAND type 1-transistor FeRAM is a promising candidate for realizing fast access time of 50ns.

NEMS switch with 30 nm-thick beam and 20 nm-thick air-gap for high density non-volatile memory applications

We developed two types of titanium nitride (TiN) based nanoelectromechanical systems (NEMS) switches with the smallest dimensions ever made by typical “top-down” complementary metal–oxide–semiconductor (CMOS) fabrication technology. NEMS cantilever switch (NCLS) and NEMS clamp switch (NCS) with 30 nm-thick TiN beam and 20 nm-thick air-gap were successfully fabricated and electrically characterized. The fabricated NCLS showed ideal on/off current characteristics with an essentially zero off current, a sub-threshold slope of less than 3 mV/decade, and an on/off current ratio over 10 5 in air ambient. Also, the NCLS exhibited an endurance of over several hundred of switching cycles under dc and ac bias conditions in air ambient. Suspended beam memory (SBM) cell array structure was suggested for high density non-volatile memory applications.

A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology

We propose a new large-scale logic test element group (TEG), called a flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and to imitate a logic LSI. We implemented a 10 Mgates FF-RAM using our 65-nm CMOS process. The FF-RAM enables us to make fail-bit maps (FBM) of logic cells because of its cell array structure as an SRAM. An FF-RAM has an additional structure to detect the open and short failure of upper metal layers. The test results show that it can detect failure locations and layers effortlessly using FBMs. We measured and analyzed it for both the cell arrays and the upper metal layers. Their results provided many important clues to improve our processes. We also measured the neutron-induced soft error rate (SER) of FF-RAM, which is becoming a serious problem as transistors become smaller. We compared the results of the neutron-induced soft error rate to those of previous generations: 180nm, 130nm, and 90nm. Because of this TEG, we can considerably shorten the development period for advanced CMOS technology.

Experimental study of carrier transport in multi-layered structures

Gate stress measurements are applied to Flash cell array structures. The counter intuitive V t shift is associated to the charge redistribution in the ONO layer. This redistribution of charge follows Poole–Frenkel conduction mechanisms. In multi-level Flash, the total charge in the nitride layer need to be minimized, and well-controlled, in order to achieve good data retention of the device.

Magnetic Random Access Memory (MRAM)

The high density and high speed nonvolatile MTJ MRAMs are reviewed from perspective of the reading and writing operation. The reading operation of the MRAM with different sensing schemes and cell array structures is discussed, in particular the reference resistance generating schemes which are introduced to maximize the cell efficiency and reading reliability. The high density, low cost cross-point cell layout structures are analyzed systematically. The writing operation modes ranging from the half-select, toggle mode, guided SAF direct writing, thermally assisted writing, to the spin transfer switching are investigated both theoretically and experimentally. The thermal factor always plays an important role in determine not only the thermal stability but also the reading and writing reliability.