Array Operation Mode Characterization of Select Gate Lateral Coupling Single-Poly Embedded Nonvolatile Memory

Abstract

This paper clarifies the reason for the specific array structure and operation methods of a select gate lateral coupling (SGLC) cell array as well as its disturbance immunity. An SGLC cell is a type of single-poly embedded nonvolatile memory that does not require any additional masks and process steps for fabrication. It shows excellent features, such as high programming speed, small cell size comparable to that of SRAM, multitime programmable, and over-erase free characteristic. However, the reasons of its operation methods and cycling limitation have not yet been clarified. We investigated the cycling effect of two types of array structures based on the unit-cell operation method. In particular, in the forward read mode, because of drain-induced barrier lowering (DIBL) that is enhanced by trapped holes at the liner nitride, $V_{T}$ of a programmed cell significantly decreased with a relatively small number of program/erase (P/E) cycles, resulting in a narrower $V_{T}$ window. By adopting the reverse read mode with source-side programming, DIBL enhancement was suppressed and a stable $V_{T}$ window was maintained during P/E cycling. Furthermore, by measuring each disturb method that works with the SGLC cell array structure and the reverse read operation mode, we confirmed that an array size larger than 128-kB sectors is possible.