Abstract
Design technology of stacked NAND type 1-transistor FeRAM has been described. With 39nm design rule feasibility study of 1Tbit memory focused on cell array structure and core circuit has been investigated. 64 layer 8k×8k stacked SGT memory cell array structure and the double ended row and column decoder with SGT have been newly introduced.From the estimation of wordline and bitline delay time this structure enables to reduce the delay time of core circuit to 5ns. Stacked NAND type 1-transistor FeRAM is a promising candidate for realizing fast access time of 50ns.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEJ Transactions on Electronics, Information and Systems
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
