Cascode Operational Transconductance Amplifier Research Articles

A 90.9 dB SNDR 95.3 dB DR Audio Delta-Sigma Modulator with FIA-Assisted OTA.

This paper presents a low-power, high-gain integrator design that uses a cascode operational transconductance amplifier (OTA) with floating inverter-amplifier (FIA) assistance. Compared to a traditional cascode, the proposed integrator can achieve a gain of 80 dB, while reducing power consumption by 30%. Upon completing the analysis, the value of the FIA drive capacitor and clock scheme for the FIA-assisted OTA were obtained. To enhance the dynamic range (DR) and mitigate quantization noise, a tri-level quantizer was employed. The design of the feedback digital-to-analog converter (DAC) was simplified, as it does not use additional mismatch shaping techniques. A third-order, discrete-time delta-sigma modulator was designed and fabricated in a 0.18 μm complementary metal-oxide semiconductor (CMOS) process. It operated on a 1.8 V supply, consuming 221 µW with a 24 kHz bandwidth. The measured SNDR and DR were 90.9 dB and 95.3 dB, respectively.

Design of carbon allotrope FET-based folded cascode operational transconductance amplifiers (FC-OTA)

ABSTRACT Throughout this study, a high-gain, low-energy folded cascode operational transconductance amplifier (FC-OTA) was modelled utilising HSPICE software. The FC-OTA designs included implementations availing CNFETs, GNRFETs, and mixed involving a combination of CNFETs with CMOS. Comparison with traditional CMOS-based FC-OTAs revealed that CNFET-based FC-OTAs exhibited considerable enhancements, displaying significant escalation in DC amplification, output resistance, average power dissipation, and CMRR. The phase margin in CNT-based FC-OTAs indicated stability. Moreover, CNT-based devices showed substantial rise in direct current amplification over GNRFET-FC-OTAs. The study further explored the operational effectiveness of proposed FC-OTAs by varying parameters such as CNT diameter, CNT pitch, and the number of CNTs, identifying optimal values that significantly enhance the FC-OTA’s performance. Comprehensive parametric and Monte Carlo analyses demonstrated OTA’s resilience to changes in supply voltage, temperature, capacitance, and mismatches. In summary, the folded cascode approach was found to enhance gain and reduce average power in CNFET-based FC-OTAs in comparison to other structural configurations.

Improvement in Sizing Constrained Analog IC via Ts-CPD Algorithm

In this work, we propose a variation of the cellular particle swarm optimization algorithm with differential evolution hybridization (CPSO-DE) to include constrained optimization, named Ts-CPD. It is implemented as a kernel of electronic design automation (EDA) tool capable of sizing circuit components considering a single-objective design with restrictions and constraints. The aim is to improve the optimization solutions in the sizing of analog circuits. To evaluate our proposal’s performance, we present the design of three analog circuits: a differential amplifier, a two-stage operational amplifier (op-amp), and a folded cascode operational transconductance amplifier. Numerical simulation results indicate that Ts-CPD can find better solutions, in terms of the design objective and the accomplishment of constraints, than those reported in previous works. The Ts-CPD implementation was performed in Matlab using Ngspice and can be found on GitHub (see Data Availability Statement).

Single-Stage Complementary Metal–Oxide–Semiconductor Operational Transconductance Amplifiers (OTAs): A Design Tutorial

This paper presents a comprehensive design tutorial for four types of single-stage operational transconductance amplifiers (OTAs): (1) five-transistor OTAs, (2) telescopic cascode OTAs, (3) folded cascode OTAs, and (4) current mirror OTAs. These OTAs serve as fundamental building blocks in analog circuits. The operational principles of each OTA are reviewed, and the key performance metrics are derived through a hand analysis. These performance metrics encompass most crucial parameters, including small-signal parameters, frequency response, input and output swing ranges, rising and falling slew rates, nonidealities, and bias circuit simplicity. All of these metrics are verified and compared using the simulation. Furthermore, the practical applications of each OTA are summarized, and a case study demonstrates the enhancement of a neural recording amplifier’s performance through appropriate OTA selection. A thorough review of the essential building blocks will become a stepping stone to design high-performance analog amplifiers across diverse applications.

Design and Analysis of High-Performance Double Recycling Folded Cascode Operational Transconductance Amplifier

Design and Analysis of High-Performance Double Recycling Folded Cascode Operational Transconductance Amplifier

Design and analysis of DTMOS based RFC with controlled positive feedback OTA using HSCCM and adaptive biasing technique

In this paper, DTMOS based recycling folded cascode with controlled positive feedback operational transconductance amplifier is introduced. The proposed Positive Feedback Recycling Folded Cascode Operational Transconductance Amplifier (PFRFC OTA) employs positive feedback which enhances and controls the dc gain of PFRFC OTA by adjusting current in feedback. The proposed PFRFC OTA also utilizes the high swing cascode current mirror (HSCCM) as active load which provides high output impedance at low power supply requirements. Moreover, the adaptive biasing is provided by using cross-coupled flipped voltage followers to the differential pair which results in remarkable improvement in gain, unity gain bandwidth and slew rate. The flipped voltage followers are also utilized to reuse the input current to drive the transistors which are connected in feedback with HSCCM. The proposed PFRFC OTA employs PMOS DTMOS transistors at the input stage which utilizes the body effect to enhance the performance of the proposed amplifier. The proposed PFRFC OTA with the second stage is also implemented to further improve the frequency response of the proposed circuit. Mentor Graphics Eldo tool with CMOS technology of 0.18 μm is used for the simulation of the proposed circuits at supply voltage of ±0.5 V. The simulation result of the proposed PFRFC OTA provides gain of 90 dB and a power consumption of 42 μW. The proposed two stage PFRFC OTA provides gain of 114.56 dB. To validate the efficiency of the proposed two stage PFRFC OTA, a tunable biquad filter is also implemented.

Design of a Configurable Third-Order Gm-C Filter Using QFG and BD-QFG MOS-Based OTA for Fast Locking Speed PLL

High-speed PLL is highly demanding with the advancement in the VLSI market. PLL performance gets affected due to bandwidth limitation. This paper presents third-order configurable transconductance capacitance ([Formula: see text]-[Formula: see text])-based loop filter for high-speed PLL. Operational transconductance amplifier (OTA) serves as a basic cell of the [Formula: see text]-[Formula: see text] filter. Quasi-floating gate (QFG) and Bulk-driven qausi-floating gate (BD-QFG) MOS-based differential input folded cascode (FC) OTAs are proposed for low-voltage operation. Here, DC gain of the BD-QFG FC OTA enhanced 5.18% than QFG FC OTA. The proposed OTAs enhanced DC gain, CMRR, UGB and FOM along with reduction in the power consumption in comparison to the state-of-art work. Further, third-order [Formula: see text]-[Formula: see text] filters are designed using both QFG and BD-QFG MOS-based OTAs and achieved [Formula: see text]3[Formula: see text]dB cut-off frequency of 16.51[Formula: see text]MHz and 17.22[Formula: see text]MHz, respectively. The proposed QFG and BD-QFG MOS-based filters achieved 22.42% and 21.53% reduction in power than the reported result, respectively. The locking time of integer-N PLL is calculated as 0.33[Formula: see text][Formula: see text]s and 0.32[Formula: see text][Formula: see text]s, respectively, through an analytical approach. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.

An ultra high slew rate recycling folded cascode OTA with 100-dB DC gain

This article presents an operational transconductance amplifier (OTA) with enhanced transconductance and slew rate. High transconductance is achieved by implementing local common-mode feedback (LCMF) in a new path. This new path also is used in providing the current splitting technique. The slew rate is significantly boosted due to a new slew rate enhancement circuit, a new quasi-floating gate (QFG) circuit and two non-linear current mirrors. The advantage of the proposed OTA is that its large-signal and small-signal figures of merits are remarkably improved compared to previous works. The post-layout simulation of the OTA is in TSMC 180 nm CMOS process. Monte Carlo and corner analyses shows the robustness of the OTA with variations of process and mismatch.

Implementation of Modified folded Cascode OTA in Different Biasings Voltages

This paper presents an optimized methodology to modified folded Cascode operational trans conductance amplifier (OTA) design. The design is done in different regions of operation, weak inversion, strong inversion and moderate inversion using the gm/ID methodology in order to optimize MOS transistor sizing. This new family of OTA designs is suitable for biomedical and healthcare circuits and systems, due to the high energy-efficiency, improved gain and low level of noise contribution, when compared to the stateof- the-art in this field. In this paper, two fully-differential implementations are presented, a first one with a double CMOS branch biased by two pairs of voltage-combiners structures in both NMOS and PMOS configurations, and a second one with folded voltagecombiners specifically targeting low voltage applications. The folded voltage-combiners biased OTA is able to operate correctly under a voltage supply down to 0.7 V with proper DC biasing. The simulation is performed in HSPICE Synopsys Tool and compared with existing designs.

A Low-Noise High-Gain Recycling Folded Cascode Operational Transconductance Amplifier Based on Gate Driven and Quasi-Floating Bulk Technique

Operational Transconductance Amplifier (OTA) is an important circuit block used in the design of filter, amplifiers and oscillators for various analog-mixed circuit systems. However, design of a low-noise, high-gain OTA with low-power consumption is a challenging task in CMOS technology owing to high-power requirements of OTA for emulating high gain. This paper represents the design of gate-driven quasi-floating bulk recycling folded cascode (GDQFB RFC) OTA which has been shown to provide low-noise operation, emulates high gain and draws very less power. The design utilizes the gate-driven quasi-floating bulk (GDQFB) technique on a recycling folded cascode structure, which enhances the transconductance of OTA and improves its performance. All the post-layout simulation results have been obtained in 0.18-μm CMOS N-well technology using BSIM3V3 device models. The obtained results indicate very high gain of 100.4 dB, gain-bandwidth of 69 kHz, phase margin of 51.9∘ with power consumption of 2.31μW from ±0.9V supply voltage. The input referred noise emulated by proposed OTA is 0.684, 0.21 and 0.0592μV/√Hz @ 1 Hz, 10 Hz and 1 kHz, respectively. The input common mode range and output voltage swing are found to be −0.402 to 0.669 V and −0.493 to 0.610 V, respectively. Corner simulations and Monte Carlo analysis have been performed to verify the robustness of the proposed OTA. The proposed OTA can be used in design of filters and amplifiers for bio-instruments, sensor applications, neural recording applications and human implants etc.

A nonlinear current mirror method for improving the slew rate of subthreshold current recycling OTAs

ABSTRACT A proposed ultra-high slew rate current recycling folded cascode OTA working in the subthreshold region is presented. By employing adaptive biasing and the proposed positive-feedback nonlinear current mirror techniques, it not only forces the charge or discharge path to enter the strong inversion region during slewing, but also provides an ultra-high output current, leading to a significant boost in the slew rate. The simulation results of the two OTAs designed in SMIC 0.18 m CMOS process demonstrate that the slew rate of our proposed OTA is enhanced 387 times than that of the conventional counterpart with the same power.

An Area- and Energy-Efficient 16-Channel, AC-Coupled Neural Recording Analog Frontend for High-Density Multichannel Neural Recordings

We present an AC-coupled modular 16-channel analog frontend with 1.774 fJ/c-s∙mm2 energy- and area-product for a multichannel recording of broadband neural signals including local field potentials (LFPs) and extracellular action potentials (EAPs). To achieve such a small area- and energy-product, we employed an operational transconductance amplifier (OTA) with local positive feedback, instead of a widely-used folded cascode OTA (FC-OTA) or current mirror OTA for conventional neural recordings, while optimizing the design parameters affecting performance, power, and area trade-offs. In addition, a second pole was strategically introduced in the LNA to reduce the noise bandwidth without an in-channel low-pass filter. Compared to conventional works, the presented method shows better performance in terms of noise, power, and area usages. The performance of the fabricated 16-channel analog frontend is fully characterized in a benchtop and an in vitro setup. The 16-channel frontend embraces LFPs and EAPs with 4.27 μVrms input referred noise (0.5–10 kHz) and 53.17 dB dynamic range, consuming 3.44 μW and 0.012 mm2 per channel. The channel figure of merit (FoM) of the prototype is 147.87 fJ/c-s and the energy-area FoM (E-A FoM) is 1.774 fJ/c-s∙mm2.

An ultra-efficient recycling folded cascode OTA based on GAA-CNTFET technology for MEMS/NEMS capacitive readout applications

This paper demonstrates an ultra-efficient recycling folded cascode (RFC) operational transconductance amplifier (OTA) as one of the cardinal blocks in most analog microsystems. Two positive feedbacks are utilized in the proposed RFC OTA to enhance the input transconductance and the output impedance. All GAA-CNTFETs are biased in the near-threshold region (VT≈0.37 V and VDD=±0.2 V) to reduce power consumption. The simulation results indicate that with CLoad = 5pF, the proposed RFC OTA shows 102 dB open-loop gain and 17.2 MHz unit gain-bandwidth with an ultra-low power consumption of 111.5nW and a reasonable slew rate response (17.3 V/µs). A capacitive readout circuit for micro-and nano-electromechanical systems (MEMS/NEMS) applications is suggested to assess the proposed RFC OTA's performance in practical applications. By utilizing an RC sensing feedback structure, the proposed transimpedance amplifier presents 155dBΩ gain with a 400 MHz bandwidth. Compared to the other counterparts, the proposed GAA-CNTFET-based TIA presents fascinating power savings 86% total average improvement) and 1.6 times total average gain improvement. Our simulation results accentuate that the proposed GAA-CNTFET-based RFC OTA is a powerful candidate for designing ultra-efficient MEMS/NEMS capacitive accelerometers readout circuits.

An Improved Comparator Based on Current Reuse and a New Frequency Compensation Technique used in an OTA for Pipeline ADCs

In this paper, a comparator and an operational amplifier considered as essential components, constituting a 10-bit 50-MHz pipeline Analog-to-Digital Converter for Wireless Local Area Network (WLAN) applications, are described and designed. All post-layout and Monte-Carlo simulations, using a 0.35[Formula: see text][Formula: see text]m CMOS AMS process technology with [Formula: see text][Formula: see text]V supply voltage and an input common-mode range of [Formula: see text][Formula: see text]V, are achieved. An improved clocked comparator with a dynamic latch, based on a switched capacitor network, using the current reuse technique for slew rate enhancement and positive feedback for offset voltage compensation, is presented. The operational amplifier, consisting of a fully differential folded cascode operational transconductance amplifier, providing high-gain and good stability, is exhibited. A new frequency compensation technique, based on active resistors, is used to improve amplifier phase-margin. The Monte-Carlo performance results of the designed clocked comparator provide an offset voltage of [Formula: see text][Formula: see text]mV with [Formula: see text][Formula: see text]mV 3[Formula: see text] deviation, a slew rate of [Formula: see text]V/ns with [Formula: see text]V/ns 3[Formula: see text] deviation, and a propagation delay of [Formula: see text][Formula: see text]ns with [Formula: see text][Formula: see text]ns 3[Formula: see text] deviation. Monte-Carlo performance results of the designed operational amplifier provide a phase-margin of [Formula: see text], and a high-gain of [Formula: see text]dB with [Formula: see text] and [Formula: see text]dB 3[Formula: see text], respectively, by using [Formula: see text] load capacitance.

DESIGN AND SIMULATION OF LOW POWER, HIGH GAIN AND HIGH BANDWIDTH CMOS FOLDED CASCODE OTA USING RECYCLING AND gm/ID TECHNIQUE

This paper includes the design of Enhanced Recycling folded cascode Operational Transconductance Amplifier (ERFC OTA) in both strong inversion and moderate inversion. The primary motivation for the design is from standard folded cascade (FC) OTA. The biased current sources are not contributing to the Transconductance (Gm) of the OTA in the usual FC OTA. In the Recycling FC OTA, the currents are recycled and the biased current sources are made to contribute to the Gm of the OTA and so the Gm is increased. Gm is further enhanced in Improved RFC OTA by creating one more high impedance dc path to the RFC architecture. The design is implemented in 90 nm UMC CMOS technology.

A DTMOS-based power efficient recycling folded cascode operational transconductance amplifier

The focus of the present study is on a recycling folded cascode (RFC) operational transconductance amplifier (OTA) in which the transconductance, as well as the slew rate of OTA, are enhanced. RFC OTA, proposed in this study, is employed using a Dynamic Threshold Voltage MOSFET (DTMOS) based differential pair with class AB operation. To achieve class AB operation, an adaptive biasing technique comprising a flip voltage follower is used which boosts the dynamic current and gain-bandwidth product of OTA. Conventional current mirrors are replaced with source degenerated non-linear current mirrors to achieve a better slew rate. The conventional and proposed RFC structures are designed and simulated in a standard 180 nm CMOS process at 1 V supply voltage. The proposed RFC OTA demonstrates a significant enhancement in the performance parameter as 11 dB improvement in the gain as well as 290% more GBW and achieves a slew rate that is nine times better compared to the conventional RFC.

A fully differential switched‐capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications

A novel switched-capacitor integrator based programmable resolution analog to digital converter (ADC) architecture is proposed. The proposed hybrid ADC architecture can be switched between successive approximation register (SAR) and delta-sigma modulator (DSM) mode in 8-bit to 15-bit resolution. A mathematical relationship showing the effect of mismatch of capacitors on ADC linearity is derived. A fully differential folded cascode operational transconductance amplifier (OTA) operating in a weak inversion region is designed using gm/ID technique with programmable unity gain bandwidth and slew rate. The designed OTA offers 83 dB DC gain. The proposed ADC, designed and laid out in UMC 180 nm standard CMOS technology, occupies an area of 0.228 mm2. The ADC resolution is programmable from 8-bit to 15-bit using a 3-bit control bus (res[2 : 0]). The hybrid ADC operates in SAR mode from 8-bit to 11-bit resolutions and as the first-order DSM with a multi-bit quantizer in 12-bit to 15-bit resolutions. The dynamic performance of the proposed ADC is verified through post-layout simulations with a supply voltage of 1.8 V. It exhibits a signal-to-noise and distortion ratio of 45–86 dB and consumes a power of 0.86–98 μW across target resolutions (8–15 bits).

Compact Continuous Time Common-Mode Feedback Circuit for Low-Power, Area-Constrained Neural Recording Amplifiers

A continuous-time common-mode feedback (CMFB) circuit for low-power, area-constrained neural recording amplifiers is proposed. The proposed CMFB circuit is compact; it can be realized by simply replacing passive components with transistors in a low-noise folded cascode operational transconductance amplifier (FC-OTA) that is one of the most widely adopted OTAs for neural recording amplifiers. The proposed CMFB also consumes no additional power, i.e., no separate CMFB amplifier is required, thus, it fits well to low-power, area-constrained multichannel neural recording amplifiers. The proposed CMFB is analyzed in the implementation of a fully differential AC-coupled neural recording amplifier and compared with that of an identical neural recording amplifier using a conventional differential difference amplifier-based CMFB in 0.18 μm CMOS technology post-layout simulations. The AC-coupled neural recording amplifier with the proposed CMFB occupies ~37% less area and consumes ~11% smaller power, providing 2.67× larger output common mode (CM) range without CM bandwidth sacrifice in the comparison.

Random offset minimization in low frequency front-end amplifiers using swarm intelligence based techniques

Random offset in amplifiers arises mainly due to random variations i.e. inherent mismatch in transistor parameters and greatly impacts its overall design specifications, especially in case of low frequency application. It must be minimized for high precision in the amplifier’s performance. A new approach for minimization of random offset voltage in amplifiers has been proposed through the use of swarm intelligence based optimization algorithms due to their derivative free nature and easy search mechanism. The approach involves firstly, modelling the random offset voltage due to mismatch between transistors parameters based on Pelgrom’s model and then minimizing the formulated model subjected to design constraints using swarm intelligence based algorithms. Two case studies are considered, firstly, a high swing Folded Cascode Operational Transconductance Amplifier (OTA) and secondly, a Recycling Folded Cascode (RFC) OTA. Comparative analysis have been performed by recording best, worst and mean data for 2500 function evaluations and also using statistical analysis such as Friedmann’s test and Mann–Whitney’s U test. The results indicate that the Hybrid Whale Particle Swarm Optimization (HWPSO) algorithm outperforms the other state of the art algorithms by giving a minimum random offset voltage of 7.2 mV and 1.452 mV with a mean rank of 1.55 and 1.75 for the 1st and 2nd case studies respectively. Validation of HWPSO results have been done by performing simulations and Monte Carlo Analysis for the two amplifiers in Cadence Virtuoso, which are found to be in close agreement with the algorithmic results.

A Low-Noise Area-Efficient Current Feedback Instrumentation Amplifier

The low-power current feedback instrumentation amplifier (CFIA) circuits using local feedback configuration are reported in the literature for biomedical applications. However, they have limitations such as low gain, higher area, and higher noise due to the need for higher source degeneration resistors (in tens to hundreds of kΩ), and higher minimum achievable bandwidth (in tens of kHz). In this paper, a low-power, low-noise CFIA using closed-loop configuration is proposed to overcome these limitations. It uses a folded cascode operational transconductance amplifier with a lower value of source degeneration resistor (in the order of few kΩ) in the input stage to reduce the noise without compromising the loop gain. As the bandwidth of the proposed CFIA is defined as unity-gain bandwidth of the CFIA’s loop gain, it can be reduced below 10 kHz without increasing area. The proposed CFIA is designed and implemented in a 0.35 µm CMOS process for a current of 9.6 µA with a supply voltage of 3 V, and its performance is evaluated through simulation. It has a gain of 34 dB, total input-referred noise of 3 µVrms, and a noise efficiency factor of 3.81. It achieves a bandwidth of 8.8 kHz using a load capacitor which is more than four times smaller than that of local CFIA. It provides an input signal swing of 16 mVpp at THD of 1% and the CMRR of 118 dB.