Design of a Configurable Third-Order Gm-C Filter Using QFG and BD-QFG MOS-Based OTA for Fast Locking Speed PLL

Abstract

High-speed PLL is highly demanding with the advancement in the VLSI market. PLL performance gets affected due to bandwidth limitation. This paper presents third-order configurable transconductance capacitance ([Formula: see text]-[Formula: see text])-based loop filter for high-speed PLL. Operational transconductance amplifier (OTA) serves as a basic cell of the [Formula: see text]-[Formula: see text] filter. Quasi-floating gate (QFG) and Bulk-driven qausi-floating gate (BD-QFG) MOS-based differential input folded cascode (FC) OTAs are proposed for low-voltage operation. Here, DC gain of the BD-QFG FC OTA enhanced 5.18% than QFG FC OTA. The proposed OTAs enhanced DC gain, CMRR, UGB and FOM along with reduction in the power consumption in comparison to the state-of-art work. Further, third-order [Formula: see text]-[Formula: see text] filters are designed using both QFG and BD-QFG MOS-based OTAs and achieved [Formula: see text]3[Formula: see text]dB cut-off frequency of 16.51[Formula: see text]MHz and 17.22[Formula: see text]MHz, respectively. The proposed QFG and BD-QFG MOS-based filters achieved 22.42% and 21.53% reduction in power than the reported result, respectively. The locking time of integer-N PLL is calculated as 0.33[Formula: see text][Formula: see text]s and 0.32[Formula: see text][Formula: see text]s, respectively, through an analytical approach. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.