Cascode Operational Transconductance Amplifier Research Articles

Novel low-voltage ultra-low-power DVCC based on floating-gate folded cascode OTA

In this paper a novel low-voltage ultra-low-power differential voltage current conveyor (DVCC) based on folded cascode operational transconductance amplifier OTA with only one differential pairs floating-gate MOS transistor (FG-MOST) is presented. The main features of the proposed conveyor are: design simplicity; rail-to-rail input voltage swing capability at a low supply voltage of ±0.5V; and ultra-low-power consumption of mere 10μW. Thanks to these features, the proposed circuit could be successfully employed in a wide range of low-voltage ultra-low-power analog signal processing applications. Implementation of new multifunction frequency filter based on the proposed FG-DVCC is presented in this paper to take the advantages of the properties of the proposed circuit. PSpice simulation results using 0.18μm CMOS technology are included as well to validate the functionality of the proposed circuit.

Novel low-voltage low-power high-precision CCII± based on bulk-driven folded cascode OTA

This paper presents possible approaches to the design of a novel low-voltage, low-power, and high-precision current conveyor of the second generation (CCII±) based on the bulk-driven folded cascode operational transconductance amplifier (OTA) with extended input common-mode voltage range. This CCII± utilizes bulk-driven differential pairs to obtain a nearly rail-to-rail input stage at a low supply voltage. The proposed conveyor operates at a low supply voltage of ±400mV with a reduced power consumption of only 64μW. A current-mode multifunction filter is presented as an application of the CCII±. This filter provides five transfer functions simultaneously, namely low-pass, band-pass, high-pass, notch, and all-pass. The filter has the following properties and advantages: it employs three bulk-driven current conveyors BD-CCII±, three grounded resistors, and two grounded capacitors, which is suitable for integrated circuit implementation. Furthermore, the input signal is connected to the low-impedance X terminal of the BD-CCII± whereas the output signals are taken from the high-impedance output terminals Z+ and Z−. Finally, the pole frequency and quality factor of the designed filter are tunable independent of each other. PSpice simulation results using the 0.18μm CMOS technology are included to prove the results.

A High-Temperature Folded-Cascode Operational Transconductance Amplifier in 0.8-μm BCD-on-SOI

The rapid growth of the hybrid electric vehicles (HEVs) has been driving the demand of high temperature automotive electronics target for the engine compartment, power train, and brakes where the ambient temperature normally exceeds 150°C. An operational transconductance amplifier (OTA) is an essential building block of various analog circuits such as data converters, instrumentation systems, linear regulators, etc. This work presents a high temperature folded cascode operational transconductance amplifier designed and fabricated in a commercially available 0.8-μm BCD-on-SOI process. SOI processes offer several orders of magnitude smaller junction leakage current than bulk-CMOS processes at temperatures beyond 150°C. This amplifier is designed for a high temperature linear voltage regulator; the higher open-loop gain of this amplifier will enhance the overall performance of a linear regulator. In addition, the lower current consumption of the OTA is critical for improving the current efficiency of the linear regulator and reducing the power dissipation at elevated temperature. A PMOS input pair folded cascode OTA topology had been selected in this work, PMOS input pair offers wider ICMR (input common-mode range) and empirically lower flicker noise compared to its NMOS counterpart. By cascoding current mirror load at the output node, the folded cascode OTA obtains higher voltage gain than the symmetrical OTA topology. The PSRR (power supply rejection ratio) is also improved. A on-chip temperature stable current reference is employed to bias the amplifier. The amplifier consumes less than 65μA bias current at 175°C. The core layout area of the amplifier is 0.16mm2 (400 μm × 400 μm).

Impact of gate–source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

In this work, we report on the significance of gate–source/drain extension region (also known as underlap design) optimization in double gate (DG) FETs to improve the performance of an operational transconductance amplifier (OTA). It is demonstrated that high values of intrinsic voltage gain (AVO_OTA) > 55 dB and unity gain frequency (fT_OTA) ∼ 57 GHz in a folded cascode OTA can be achieved with gate-underlap channel design in 60 nm DG MOSFETs. These values correspond to 15 dB improvement in AVO_OTA and three fold enhancement in fT_OTA over a conventional non-underlap design. OTA performance based on underlap single gate SOI MOSFETs realized in ultra-thin body (UTB) and ultra-thin body BOX (UTBB) technologies is also evaluated. AVO_OTA values exhibited by a DG MOSFET-based OTA are 1.3–1.6 times higher as compared to a conventional UTB/UTBB single gate OTA. fT_OTA values for DG OTA are 10 GHz higher for UTB OTAs whereas a twofold improvement is observed with respect to UTBB OTAs. The simultaneous improvement in AVO_OTA and fT_OTA highlights the usefulness of underlap channel architecture in improving gain–bandwidth trade-off in analog circuit design. Underlap channel OTAs demonstrate high degree of tolerance to misalignment/oversize between front and back gates without compromising the performance, thus relaxing crucial process/technology-dependent parameters to achieve ‘idealized’ DG MOSFETs. Results show that underlap OTAs designed with a spacer-to-straggle (s/σ) ratio of 3.2 and operated below a bias current (IBIAS) of 80 µA demonstrate optimum performance. The present work provides new opportunities for realizing future ultra-wide band OTA design with underlap DG MOSFETs.

Recent Advances on the Design of High-Gain Wideband Operational Transconductance Amplifiers

Feed-forward techniques are explored for the design of high-frequency Operational Transconductance Amplifiers (OTAs). For single-stage amplifiers, a recycling folded-cascode OTA presents twice the GBW (197.2 MHz versus 106.3 MHz) and more than twice the slew rate (231.1 V/s versus 99.3 V/s) as a conventional folded cascode OTA for the same load, power consumption, and transistor dimensions. It is demonstrated that the efficiency of the recycling folded-cascode is equivalent to that of a telescopic OTA. As for multistage amplifiers, a No-Capacitor Feed-Forward (NCFF) compensation scheme which uses a high-frequency pole-zero doublet to obtain greater than 90 dB DC gain, GBW of 325 MHz and better than phase margin is discussed. The settling-time- of the NCFF topology can be faster than that of OTAs with Miller compensation. Experimental results for the recycling folded-cascode OTA fabricated in TSMC 0.18 m CMOS, and results of the NCFF demonstrate the efficiency and feasibility of the feed-forward schemes.

Feedforward-Regulated Cascode OTA for Gigahertz Applications

A very high-frequency operational transconductance amplifier (OTA) with a new feedforward-regulated cascode topology is demonstrated in this paper. Experimental results show a bandwidth of 10 GHz and a large transconductance of 11 mS. A theoretical analysis of the OTA is provided which is in very good agreement with the measured results. We also carry out a Monte Carlo simulation to determine the effect of transistor mismatches and process variations on the transconductance and input/output parasitic capacitances of the OTA. The linearity and intermodulation distortion properties of the OTA, which are of particular interest in microwave applications, are experimentally determined using a purpose-built single-stage amplifier. For high-frequency demonstration purposes we built a larger circuit: an inductor less microwave oscillator. The fabricated oscillator operates at 2.89 GHz and has a significantly larger output voltage swing and better power efficiency than other inductor less oscillators reported in the literature in this frequency range. It also has a very good phase noise for this type of oscillators: -116 dBc/Hz at 1-MHz offset.

CMOS CCII– based on modified dual output-OTA for high frequency applications

A negative CMOS second generation current conveyor (CMOS CCII–) based on modified dual output CMOS folded cascode operational transconductance amplifier (CMOS DO-OTA) is presented. The proposed folded cascode CMOS DO-OTA with attractive features for high frequency operation such as high output impedance, wide bandwidth, high slew rate, with low power consumption is used in the realisation. The proposed CMOS DO-OTA and CMOS CCII– with high performance parameters can be used in many high frequency applications. The proposed CMOS CCII– achieves 1.37 GHz (−3 dB BW), 1.8 ns settling time, 48 V/μs slew rate, and low power consumption around 3.25 mW for ±2.5 V supply. P-Spice simulation results are included for 0.5 μm MIETEC CMOS technology.

CMOS linear programmable transconductor suitable for adjustable Gm-C filters

A novel CMOS linear programmable transconductor is presented. It is based on a telescopic cascode operational transconductance amplifier with source degeneration implemented by means of highly linear tunable active resistors. The transconductor has been designed in a 0.5 µm CMOS technology featuring a third-order intermodulation (IM3) of −54.8 dB at 10 MHz for a 1 Vpp output voltage. Its feasibility for Gm-C filter design has been experimentally validated with a 1 MHz tunable third-order Chebyshev lowpass filter suitable for Bluetooth applications.

A novel feed-forward compensation technique for single-stage fully-differential CMOS folded cascode rail-to-rail amplifier

This paper presents a novel active and passive mixed feed-forward compensation technique for single-stage CMOS folded-cascode rail-to-rail operational trans-conductance amplifiers (OTA). Simulations using 0.5 μm Agilent CMOS process parameters indicate a phase margin of around 82° with an unity gain bandwidth of 320 MHz (@1.17 pF capacitive load including the device parasitics). Also, the compensated OTA provided over 60 dB DC-gain with rail-to-rail output voltage swing as well as wide input common-mode range. This ensures optimum step response (fast and accurate settling without ringing) for the feedback amplifier in switched-capacitor signal processing applications. An improved ``fast sensing'' common-mode feedback circuit with high common-mode gain is also used for the single-stage cascode OTA.

Improved design criteria of gain-boosted CMOS OTA with high-speed optimizations

A comprehensive study on gain-boosted regulated cascode operational transconductance amplifiers (OTA) is discussed. These amplifiers are usually good for power optimized high-speed designs. However, location of an additional pole-zero pair in the transfer function makes the transient response much slower than expected. A new design is proposed along with the systematic approach which get rid of this pole-zero pair and deliberately puts a pair of complex poles to make the design faster.

Low-voltage, low-power and high gain cmosota using active positive feedback with feed forward and FDCM techniques

A low voltage, high dc gain and wideband load compensated cas code operational transconductance amplifier (OTA), using an active positive feedback with feed forward technique and frequency-dependent current mirrors (FDCM), is presented and analyzed. Such techniques stand as a powerful method of gain bandwidth and phase margin enhancements. In this paper, a frequency-dependent current mirror, whose input impedance increases with frequency, is used to form the feed forward path at the input of the current mirror with a feed forward capacitor. By using these techniques, the gain bandwidth product of the amplifier is improved from 115 MHz to 194 MHz, the phase margin is also improved from 85? to 95? and the gain is enhanced from 11 dB to 93 dB. This amplifier operates at 2.5 V power supply voltage drives a capacitive load of 1pF and gives a power dissipation of 7 mW. The predicted performance is verified by simulations using HSPICE tool with 0.8 fim CMOS AMS parameters.

1-V power supply CMOS cascode amplifier

We design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69-dB DC gain, a 2-MHz bandwidth, and compatible input- and output voltage levels at a 1-V power supply. This is done by a novel, current driven bulk (CDB) technique, which reduces the MOST threshold voltage by forcing a constant current though the transistor bulk terminal. We also look at limitations and improvements of this CDB technique.

A CMOS digitally programmable class AB OTA circuit

A new low-voltage CMOS digitally programmable operational transconductance amplifier (OTA) circuit is presented. The circuit utilizes simple class AB voltage buffers to provide a non-slew-rate-limited performance with low standby power consumption. The OTA can be digitally programmed to maintain a constant settling time for different load capacitors without increasing the standby power consumption, Experimental results from a 1.2-/spl mu/m chip and comparisons with the regular folded cascode OTA circuit are given. The proposed circuit power consumption is found to be less than one third of a regular folded cascode OTA when driving a load capacitance of 35 pF. For the same power consumption level of 240 /spl mu/A, the new circuit achieves a slew rate more than 10 V//spl mu/s while the traditional folded cascode fails to settle.

Non-stationary noise responses of some fully differential on-chip readout circuits suitable for CMOS image sensors

CMOS active-pixel image sensors, as well as charge-coupled devices, generate both white noise and 1/f/sup /spl alpha//-noise over several decades depending on biasing current, operating temperature, and the characteristics of the process used, limiting the detector dynamic range. Three readout circuits, based on a fully differential cascode operational transconductance amplifier, designed and realized on a standard CMOS 0.7-/spl mu/m single polysilicon/double metal process, are proposed for CMOS active-pixel imagers. The first is an uncompensated switched capacitor (SC) voltage amplifier; the second, an offset compensated SC amplifier; and the third, a commutable bandpass filter. All three amplifiers allow correlated double sampling and double delta sampling for pixel and column fixed pattern noise suppression, respectively. The amplifiers offer up to 10-Mpixels/s readout rates. A detailed theoretical analysis of the amplifiers response to white noise and low-frequency excess noise is given, considering nonstationary nature of the output signals. An original method based on diffusive Markovian representation of 1/f/sup /spl alpha//-noise is used. The theoretical results are compared with experimental data.