Cascode Low Noise Amplifier Research Articles

Single-Input Multiple-Output (SIMO) Cascode Low-Noise Amplifier with Switchable Degeneration Inductor for Carrier Aggregation.

This paper presents a single-input multiple-output (SIMO) cascode low-noise amplifier with inductive degeneration for inter- and intra-band carrier aggregation. The proposed low-noise amplifier has two output ports for flexible operation in carrier aggregation combinations for band 30 and band 7. However, during inter- and intra-band operation, gain variation occurs depending on the output mode. To compensate for this, a switching circuit is proposed to adjust the degeneration inductor, optimizing gain performance for both modes. The switching operation can minimize the control for the dynamic range in the receiver system to support carrier aggregation. The designed low-noise amplifier was fabricated using a 65 nm CMOS process, occupying an area of 2.1 mm2. In inter-band operation, the small-signal gain was measured by 18.9 dB for band 30 and 18.6 dB for band 7, with the noise figures of 1.03 dB and 1.07 dB, respectively. For intra-band operation, the small-signal gain was 17.3 dB and 17.2 dB, with the noise figures of 1.3 dB and 1.41 dB. The IIP3 values were measured by -7.6 dBm and -6.7 dBm for inter-band, and -6.3 dBm and -6.2 dBm for intra-band. Power consumption was 8.04 mW and 7.68 mW in inter-band, and 17.04 mW and 17.64 mW in intra-band depending on the output configuration.

Comparison of single event effect on cascoded low noise amplifier performance metrics for two different frequencies

This manuscript examines the impact of single event effects (SEEs) on the well-known cascoded low noise amplifier (LNA) topology connected with an inter-stage inductor sandwiched between the common source (CS) and common gate transistors for boosting the LNA parameters (i.e., gain, etc). In this article, we have considered that the LNA operates at two different frequencies, such as 10 and 30 GHz, in a radiation-prone environment. The effect of SEEs is analyzed in two ways: (i) non-applying a RF input with dc voltage only, and (ii) applying a RF input with dc bias voltage. The first analysis uses basic integration to evaluate the collected charge (QCollected) for a drain terminal momentary current spike with a suitable time period, and the second analysis estimates the LNA output discontinuity (distortion) using a spectrogram (short-time FFT) to determine the radiation strikes on the cascoded LNA. The collected charge is calculated in the temporal analysis, and the discontinuity of LNA’s RF output is analysed using the spectrogram in the frequency domain analysis. From the temporal and frequency analysis, the LNA that operates at a lower frequency (10 GHz) provides more discontinuity in LNA output (causing more disturbance) than the LNA that operates at a higher frequency (30 GHz).

A Gm -Boosting Technique for Millimeter-Wave Low-Noise Amplifiers in 28-nm Triple-Well Bulk CMOS Using Floating Resistor in Body Biasing

This paper presents a simple yet effective <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$ </tex-math></inline-formula> -boosting technique for improving gain and noise performance of millimeter-wave (mm-wave) low-noise amplifiers (LNAs) comprising triple-well transistors typically found in the modern bulk CMOS processes. The proposed technique uses a resistor that connects the p-well and deep n-well terminals of the triple-well transistor, leaving the terminals floating instead of conventionally connecting them to the ground and supply voltage. This arrangement exploits a leakage current through a diode formed between the drain/source and p-well of each transistor, thus autonomously setting its bulk potential for increased transconductance, while ensuring its robustness to the process variation. The improved isolation between the p-well and the substrate further improves the gain and noise performance. We provide a theoretical analysis of this floating resistor-based body biasing method and support it with simulation results. For experimental validation, a two-stage cascode LNA was designed and fabricated in 28-nm bulk CMOS. The measurement results show that 3.3–4dB noise figure (NF) and 19.1–16.1dB gain are achieved at 24.7–29.5GHz. To ensure a fair comparison, another identical LNA with the normally expected triple-well biasing was also fabricated. The proposed method reveals a 0.6dB improvement in minimum NF and an additional ~3.5dB gain without any significant linearity degradation.

An improved cascode common-source LNA with inductive source degeneration for RF applications

This paper presents a novel structure to enhance the power gain (S21) of the conventional cascode common-source (CS) low-noise amplifier (LNA) with inductive source degeneration. The proposed LNA has an extra transistor and a capacitor in comparison with the conventional structure. The additive transistor significantly increases the S21 of the conventional cascode CS LNA with inductive source degeneration with the same DC power consumption (PDC), third-order input intercept point (IIP3), area, and slightly lower noise figure (NF). The utilized capacitor is used to improve the IIP3 of the proposed LNA. The power gain improvement of the proposed LNA has been validated by both theoretical analysis and extensive post-layout simulation results. The proposed and conventional LNAs have been designed in TSMC 180 nm CMOS technology. The post-layout simulation results of the proposed LNA are 2.42 dB NF, S21 of 15.55 dB, and 0.84 dBm IIP3 while consuming 3.2 mW from 1.2 V power supply. The simulated S21 of the proposed LNA is about 2.55 dB (34.2 %) larger than the conventional cascode LNA with the same other performance parameters. Also, the achieved figure-of-merit (FoM) of the proposed LNA is substantially larger than the conventional cascode CS LNA with inductive source degeneration.

A 21–41-GHz Common-Gate LNA With TLT Matching Networks in 28-nm FDSOI CMOS

A wideband common-gate (CG) cascode low-noise amplifier (LNA) is demonstrated with a 28-nm fully depleted silicon on insulator (FDSOI) CMOS process. Wide bandwidth is achieved with a CG structure in the first stage and tightly coupled ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k=0.86$ </tex-math></inline-formula> ) transmission line transformer (TLT) matching networks. A gm-boosting technique with cross-coupled capacitors improves the gain and noise figure (NF) of the CG amplifier. A high-input 1-dB gain compression point (IP1 dB) can be achieved by introducing an inter-stage inductor at the second-stage cascode amplifier. The LNA shows 19.3 dB gain, 3.1 dB NF, 19.8 GHz (63%) of 3 dB bandwidth, and −15.7 dBm IP1 dB at 28 GHz.

A two stage cascode LNA using modified derivative superposition technique in [formula omitted] HBT with an IIP3 of 2 dBm and NF of 4.8 dB for IEEE 802.11ad standard

A two stage cascode Low Noise Amplifier (LNA) is designed in 130 nm SiGe HBT. The work focuses on achieving a low Noise Figure (NF), high linearity, and high gain for the LNA in the frequency band of 57.24 GHz-65.88 GHz to be operated in all the four channels of IEEE 802.11ad standard. A modified Derivative SuperPosition technique is used in the first stage of the cascaded LNA to improve the linearity of the circuit. Post layout Electromagnetic (EM) simulation results of the proposed LNA achieves a peak gain of 20.19dB at 59.5GHz, linearity (IIP3) of 2dBm at the maximum gain and also achieved a NF of 4.1dB - 4.8dB in the operating band of frequency. DC power consumption of the proposed circuit is 9.2mW from a supply voltage of 1.2V, with an area occupancy of 311μm×298μm.

Design of a Source Degenerated Cascode Stage Low Noise Amplifier for 5G Applications

Low Noise Amplifier (LNA) is the most critical part of a receiver front end in terms of the receiver performance. The performance tradeoff among input matching, noise figure, gain, and linearity are analyzed in detail. The LNA finds its application at Portable GPS Receiver, BLE, Zigbee, NFC, WiFi, Wireless Sensor Network, RFIC operating at 2.4GHz frequency. Millimeter wave communication is an evolving technology for bandwidth demanding 5G wireless application. A high gain and linear narrowband cascode Low Noise Amplifier (LNA) operating at 2.18GHz to 2.47GHz is proposed. To demonstrate design methodology, a narrow-band source degenerated cascode LNA is designed and simulated in a standard 90nm CMOS process to operate in the 2.4 GHZ band. The LNA achieves a voltage gain of 5.38dB, Noise figure of 4.1127dB, and from 3.2 V supply voltage. Proper input and output impedance matching have been performed to achieve the input return loss of -14 dB (S11) and output return loss of -19.72 dB (S22). Simulation study has been done using Cadence spectre.

The Development of Cascode Low Noise Amplifier with Double Feedback Technique Architecture for Wireless Communication

The paper aims to develop a new cascode low noise amplifier (LNA) by using double feedback technique architecture for wireless communication especially for long term evolution (LTE). The objective of this article is to display the improved performance of gain by minimizing noise figures with innovative techniques for the realization of Long Term Evolution (LTE). The innovation technique with implementation double feedback technique architecture outlines the possibility to improve the performance in various parameters such as bandwidth, stability, gain, noise figure, power consumption and complexity. The realization using cascode LNA is verified by using FHX76LP Super Low Noise HEMT that operate at 5.8 GHz in compliant with LTE standard. The Advance Design System (ADS) software is used to obtain characteristics for collecting data in a smith chart and s-parameter generated by simulation. The cascode LNA with the double feedback technique achieves an average gain of 20.887 dB with a noise figure of 0.341 dB. The input return loss and output return loss are – 14.354 dB and – 11.879 dB respectively. The outcome of this work will contribute to providing a better wireless signal receiver especially for the LTE standard and it potentially addressing wireless communication issues in rural areas.

Design of Ka-band broadband low-noise amplifier using 100nm gate-length GaN on silicon technology

Due to the high breakdown voltage and better linearity of gallium nitride (GaN) high electron mobility transistor (HEMT), GaN based RF front-end is widely researched and studied. In this paper, a Ka-band cascode low-noise amplifier (LNA) designed with 100nm gate-length GaN-on-silicon technology is presented. With novel methods such as the introduction of high-pass filters and standing wave filtering capacitors, the LNA achieves a stable gain of 21-22.8dB and a noise figure (NF) of 0.9-1.3dB from 22GHz to 38GHz. The input and output return loss are better than-10dB in band of concern. This LNA occupies an area of 2.3mm × 0.9mm and consumes 265-mW DC power. Compared with silicon-on-insulator (SOI), indium phosphide (InP) and gallium arsenide (GaAs) LNAs, the proposed GaN LNA exhibits better performance of linearity, as well as competitive gain and NF.

Design of High Performance Low-Noise Amplifier Circuit Based on Complementary Metal Oxide Semiconductor Technology

This paper designs a body-biased (BB) differential cascode low-noise amplifier (LNA) with current bias (CR) and capacitor cross-coupling (CCC) technology that meets the bandwidth requirements of 5 GHz wireless applications. In the design, the CCC technology in the differential cascode topology is used to effectively suppress the common mode noise, thereby improving the noise figure. The series resonant network eliminates parasitic capacitance at the input and output ends, thereby improving the power transmission efficiency. The CR technology formed by the intermediate capacitor shares the DC current input to the output device, thereby increasing the gain. This paper uses BB technology in the design to lower the threshold of the cascode device and improve the transconductance, which further improves the gain and reduces the power consumption. The CCC technology used in the paper improves linearity by eliminating the non-linear components present in the input device, which will not interfere with the transconductance of the output stage. This article has obtained excellent performance parameters including gain, noise figure (NF) and linearity without affecting the power consumption, integration and cost of the proposed design.

A 0.75 V Sub-mW CMOS LNA employing transmitted signal suppression technique in a full-duplex wireless brain-machine interface transceiver

This paper presents a sub-milliwatt (sub-mW) low-voltage CMOS low-noise amplifier (LNA) that can be utilized in a full-duplex transceiver without using duplexer. The topology of the proposed LNA includes a wideband RLC network to suppress and isolate the receiver from a high-power ultra-wideband transmitted signal. This feature is comparable to other reported LNAs, which are only applicable to a narrowband signal instead of a wideband signal. In addition, the combination of a source-degenerated cascode LNA with an inverter-based LNA in the proposed topology achieves an ultra-low-voltage low-power operation with a 0.75 V bias voltage. Analytical results and the circuit implementation in a 180 nm CMOS technology verify that the proposed LNA presents an noise figure (NF) of less than 3.45 dB over a 200 MHz bandwidth at a carrier frequency of 2.4 GHz. Simulation results also demonstrate a 14 dB gain (S21), less than −11 dB input return loss (S11) and 50 dB transmitted signal attenuation rather than the desired signal. The power consumption is only 980 μW at a 0.75 V supply. The input-referred third-order intercept point (IIP3) is about −8 dBm, and the chip occupies an area of 0.37 mm2.

Cascode Low Noise Amplifier (LNA) with Negative Feedback for Long Term Evolution (LTE)

Every now and then communication technology continuing to evolved to fulfil the market especially in mobile traffics of wireless technology demanding for high-rise data rates affecting radio frequency bandwidths to affirming specific performance. Utilizing unlicensed bandwidths of 5.8 GHz, the cascode low noise amplifier (LNA) enable to associate with long term evolution (LTE) standard without detracting degradation of service aspects. Considering LNA that positioned as a front-end in receiver block system in managing transmit the signal it benefit the LTE RF requirement become novelty in this design that plays crucial role. This paper focuses on designing and analysis of cascode low noise amplifier (LNA) adopted negative feedback and T-matching network at the input and output ports to emphasize trade-offs between parameters of gain, noise figure, sensitivity and stability. Pseudomorphic High Electron Mobility Transistor (PHEMT) FHX76LP manufactured by Eudyna Devices Inc is selected and the design is stimulated by using Advance Design System tool (ADS). From the analysis resulting LNA shows a maximum gain (S21) of 20.199 dB and return loss (S12) of −23. 585 dB with minimum noise figure of 0.360 dB with 2V supply. Meanwhile, the input reflection (S11) and output return loss (S22) are −11. 101 dB and −13. 714 dB respectively.

Full D-Band Transmit–Receive Module for Phased Array Systems in 130-nm SiGe BiCMOS

This letter presents a D-band (110 to 170 GHz) transmit- receive module in 0.13-μm silicon-germanium (SiGe) BiCMOS for phased-array applications. The module includes single-pole double throw (SPDT) switches, a low noise amplifier (LNA), a power amplifier (PA), and two variable gain amplifiers (VGAs). A broadband quarter-wave SPDT is designed with power handling capacity of 17 dBm and a state-of-the-art insertion loss of 2 dB at 140 GHz. The three-stage cascode LNA and PA and the two-stage phase-compensated VGA cover the entire D-band. In the receive mode, the module has a measured peak gain of 28.3 dB with a 3-dB bandwidth (BW) of 110-170 GHz, along with a minimum noise figure (NF) of 9 dB (at 120 GHz) and an IP1dB of -21 dBm. In the transmit mode, the peak gain is 22.4 dB within a 3-dB BW of 113-170 GHz, while the OP1dB is 7 dBm and the Psat 9.5 dBm at 140 GHz.

Single and double‐gate based AlGaN/GaN MOS‐HEMTs for the design of low‐noise amplifiers: a comparative study

In this study, a 60 nm gate length double-gate AlGaN/GaN/AlGaN metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT) is proposed and different electrical characteristics, such as DC, small-signal, radio-frequency (RF) and high-frequency noise performances of the devices are characterised through TCAD device simulations. The results of double-gate MOS-HEMT are compared with the TCAD simulation results as well as with available experimental data of single-gate AlGaN/GaN MOS-HEMT having a similar gate length available from the literature. It is observed that the double-gate AlGaN/GaN/AlGaN MOS-HEMT shows good sub-threshold slope, improved ON current, short-channel effect immunity, improved RF and noise performance. A look-up table-based Verilog-A model is developed for both devices and the models are incorporated into the Cadence EDA tool to utilise the proposed device in circuit simulations. The Verilog-A model is applied to design a 1–20 GHz wideband feedback cascode low-noise amplifier (LNA). Performance variability of LNA due to single- and double-gate MOS-HEMT is also investigated.

Performance Assessment of CMOS circuits using III-V on Insulator MOS Transistors

In this work, with the help of extensive technology computer-aided design simulations, we report a comprehensive study of MOSFET based circuit design using ultra-thin body III-V on-insulator (OI) CMOS transistors. We demonstrate the circuit performance of III-V CMOS by combining InAs-OI n-channel and GaAs-OI junction-less p-channel transistors. The performance metrics of different circuits designed using III-V transistors are also compared with III-V/Germanium and Silicon-on-insulator (SOI) based CMOS logic. CMOS inverter circuit designed using III-V/Ge (InAs-OI/GeOI) CMOS shows 51% and 17% reduction in rise and fall time compared to SOI CMOS. The oscillation frequency of the ring oscillator designed using III-V/Ge (InAs-OI/GeOI) and III-V (InAs-OI/GaAs-OI) CMOS logic is approximately three times and two times higher than SOI based design. The unity-gain bandwidth of the inverting amplifier using III-V/Ge (InAs-OI/GeOI) and III-V (InAs-OI/GaAs-OI) architecture is 22 times and 9.5 times higher compared to SOI CMOS based circuit. Static noise margin (SNM) of conventional six-transistor (6-T) SRAM cell is also analyzed during hold operation. Due to the poor electrostatic integrity of III-V transistors, degradation in SNM is observed compared to its SOI counterparts. The cascode low noise amplifier (LNA) circuit designed using InAs-OI transistor shows the higher gain and low noise figure at the same operating frequency compared to the SOI transistor-based LNA.

Optimal Design of Ultra-Low-Power 2.4 GHz LNA for IEEE 802.15.4/Bluetooth Applications

In this paper, an evolutionary computation-based optimal design of low power, high gain inductive source degenerated CMOS cascode low noise amplifier (LNA) circuit is presented for 2.4[Formula: see text]GHz frequency. The main challenge for the design of radio frequency (RF) LNAs at nanometer range is the thermal noise generated in the short-channel MOSFETs. The short-channel effects (SCEs), such as velocity saturation and channel-length modulation, are considered for the design of CMOS LNA. The evolutionary algorithm taken for this work is Moth-Flame Optimization (MFO) algorithm. MFO is utilized for the optimization of noise figure (NF) while satisfying all the other design performance parameters like gain, matching parameters at input/output, power dissipation, linearity, stability. Optimal values of the sizes of the transistors and other design parameters in designing the LNA circuit are also obtained from the MFO algorithm. The CMOS LNA circuit is designed by using MFO-based optimal design parameters in CADENCE software with a standard 0.18[Formula: see text][Formula: see text]m CMOS process. The designed LNA shows a gain of 15.28[Formula: see text]dB, NF of 0.376[Formula: see text]dB, the power dissipation of 936[Formula: see text][Formula: see text]W and IIP3 of [Formula: see text][Formula: see text]dBm at 2.4[Formula: see text]GHz. The designed LNA achieves better trade-off which results in an FOM of 42.3[Formula: see text]mW[Formula: see text] and may be useful in the receiver module of IEEE 802.15.4 for WLAN applications.

A Novel Design and Optimization Approach for Low Noise Amplifiers (LNA) Based on MOST Scattering Parameters and the gm/ID Ratio

This work presents a new design methodology for radio frequency (RF) integrated circuits based on a unified analysis of the scattering parameters of the circuit and the gm/ID ratio of the involved transistors. Since the scattering parameters of the circuits are parameterized by means of the physical characteristics of transistors, designers can optimize transistor size and biasing to comply with the circuit specifications given in terms of S-parameters. A complete design of a cascode low noise amplifier (LNA) in MOS 65 nm technology is taken as a case study in order to validate the approach. In addition, this methodology permits the identification of the best trade-off between the minimum noise figure and the maximum gain for the LNA in a very simple way.

IMPROVED PERFORMANCE OF LNA USING HIGH QUALITY FACTOR PGS ON-CHIP SPIRAL INDUCTORS

This paper presents a detailed study of on-chip spiral inductors with patterned ground shield (PGS) inserted between the spiral inductorand the silicon substrate. This new design has been implemented in source degeneration cascode lownoise amplifier (LNA) circuit to show how the PGS inductors improve the performance of the circuit. An operation in 1.8V supply voltage, source degeneration cascode LNA structure was studied with both technology and PGS inductors. In this paper, the Agilent ADS (Advanced Design System) simulation software and TSMC 0.18μm CMOS process parameters were adopted to achieve the low-cost characteristics and high integration to fit the performance of 2.4 GHz LNA design under IEEE 802.11a specification.According to the co-simulation results, the forward gain (S21) improved from 13.432 to 21.474 dB, and the (S12)is below the typical value of -15dB. The input impedance (S11) and the output impedance (S22) also represented good performance. In addition, the minimum noise figure was quite good. Thus, the LNA circuit with PGS inductorswas better in the availability and the possibility of 802.11a specification.

Design of X-Band Low Noise Amplifier For Radar Applications

This paper presents an analysis for a single stage Low Noise Amplifier (LNA) for X-band radar application. The LNA is designed using commercially Pseudomorphic High Electron Mobility Transistor (P-HEMT). The LNA is designed to achieve low noise figure, high gain and a better matching to 50 Ω at both input and output terminals. Cascaded and cascoded circuit topologies were implied to achieve the targeted requirements. In addition, negative feedback technique is utilized to increase the operating bandwidth. The circuit is designed and simulated using Advanced Design System (ADS) tools. The design showed good dynamic range with moderate gain. The cascode LNA resulted in better noise figure (NF).

A single power supply 0.1-3.5 GHz low noise amplifier design using a low cost 0.5 μm d-mode pHEMT process

Design and testing results of a single power supply wide-band low noise amplifier (LNA) based on low cost 0.5 ?m D-mode pHEMT process are presented. It is shown that the designed cascode LNA has operating frequency range up to 3.5 GHz, power gain above 15 dB, noise figure below 2.2 dB, output linearity above 17 dBm and power consumption less than 325 mW. Potential immunity of the LNA to total ionizing dose and destructive single event effects exceed 300 krad and 60 MeV?cm2/mg respectively.