Abstract
This work presents a new design methodology for radio frequency (RF) integrated circuits based on a unified analysis of the scattering parameters of the circuit and the gm/ID ratio of the involved transistors. Since the scattering parameters of the circuits are parameterized by means of the physical characteristics of transistors, designers can optimize transistor size and biasing to comply with the circuit specifications given in terms of S-parameters. A complete design of a cascode low noise amplifier (LNA) in MOS 65 nm technology is taken as a case study in order to validate the approach. In addition, this methodology permits the identification of the best trade-off between the minimum noise figure and the maximum gain for the LNA in a very simple way.
Highlights
The low noise amplifier (LNA) is considered a crucial component in wireless communication systems
The S-parameters of the circuit are parameterized by means of the MOS gm/ID ratios, allowing designers to choose the latter in order to optimize transistor size and bias to comply with the circuit specifications
The same procedure is executed in order to obtain the S-parameters for the common gate configuration
Summary
The low noise amplifier (LNA) is considered a crucial component in wireless communication systems. Based on these authors’ previous works, this paper presents a comprehensive description of such a methodology for RF circuit design In this strategy, the S-parameters of the circuit are parameterized by means of the MOS gm/ID ratios, allowing designers to choose the latter in order to optimize transistor size and bias to comply with the circuit specifications. The design space exploration of a complete cascode LNA in CMOS 65 nm technology is reported, considering the amplifier gain (G), noise figure (NF), and stability Stern factor (K) as its most relevant design specifications This approach allows the identification of the best trade-off between the minimum noise figure and maximum gain for the LNA in a very simple way.
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