Carrier Stored Trench Bipolar Transistor Research Articles

High performance carrier stored trench bipolar transistor with dual shielding structure

We propose a novel high performance carrier stored trench bipolar transistor (CSTBT) with dual shielding structure (DSS-CSTBT). The proposed DSS-CSTBT features a double trench structure with different trench profiles in the surface, in which a shallow gate trench is shielded by a deep emitter trench and a thick oxide layer under it. Compared with the conventional CSTBT (con-CSTBT), the proposed DSS-CSTBT not only alleviates the negative impact of the shallow gate trench and highly doped CS layer on the breakdown voltage (BV), but also well reduces the gate-collector capacitance C GC, gate charge Q G, and turn-off loss E OFF of the device. Furthermore, lower turn-on loss E ON and gate drive loss E DR are also obtained. Simulation results show that with the same CS layer doping concentration N CS = 1.5 × 1016 cm−3, the BV increases from 1312 V of the con-CSTBT to 1423 V of the proposed DSS-CSTBT with oxide layer thickness under gate (T og2) of 1 μm. Moreover, compared with the con-CSTBT, the C GC at V CE of 25 V and miller plateau charge (Q GC) for the proposed DSS-CSTBT with T og2 of 1 μm are reduced by 79.4% and 74.3%, respectively. With the V GE increases from 0 V to 15 V, the total Q G for the proposed DSS-CSTBT with T og2 of 1 μm is reduced by 49.5%. As a result, at the same on-state voltage drop (V CEON) of 1.55 V, the E ON and E OFF are reduced from 20.3 mJ/cm2 and 19.3 mJ/cm2 for the con-CSTBT to 8.2 mJ/cm2 and 9.7 mJ/cm2 for the proposed DSS-CSTBT with T og2 of 1 μm, respectively. The proposed DSS-CSTBT not only significantly improves the trade-off relationship between the V CEON and E OFF but also greatly reduces the E ON.

High voltage carrier stored trench bipolar transistor with common anode polysilicon diodes gate structure for low Miller capacitance and low electromagnetic interference noise

A novel 3300 V high voltage carrier stored trench bipolar transistor (CSTBT) with common anode polysilicon diodes gate structure (CAPD-CSTBT) is proposed. The PN junctions and N+ emitter region in the polysilicon gate structure are beneficial for reducing the Miller capacitance by 88.1% and the input capacitance by 26.0%, while due to the polysilicon PN junction barrier, the forward and reverse gate bias voltage will not be affected. As a result, the transient energy loss could be decreased by 32.2% with the same range of R g. Since the displacement current is shielded by the embedded emitter on the bottom of the CAPD gate structure, the (dI CE /dt)max/I Load is lower than that of the Fin-P-CSTBT by 81.8% on average with the same range of turn-on energy loss. Furthermore, the proposed structure features a 58.7% lower (dV KA /dt)max/V cc value for the free-wheeling diode on average. By Fourier transformation, the proposed structure represents lower amplitudes for the I CE and V KA spectrums during the turn-on period, which is a drastic suppression of electromagnetic interference noise.

High performance floating p‐well carrier stored trench bipolar transistor with L‐shaped shield gates

A novel floating p-well carrier stored trench bipolar transistor with L-shaped shield gates (LSG-FP-CSTBT) is proposed in this Letter. The proposed device features combinatorial L-shaped shield gates with a thick oxide layer in the lower part of the trench. Numerical analysis results show that compared to the conventional FP-CSTBT, the shield effect provided by the LSGs not only improves the trade-off relationship between the on-state voltage drop ( V CEON ) and turn-off loss ( E OFF ), but also improves the trade-off relationship between the turn-on loss ( E ON ) of the device and reverse recovery d V AK / d t of the antiparallel freewheeling diode. Therefore, improved device performance and reduced electromagnetic interference noise are obtained.

A Novel Silicon Carbide Accumulation Channel Injection Enhanced Gate Transistor With Buried Barrier Under Shielding Region

A silicon carbide (SiC) injection enhanced gate transistor with accumulation channel (AC-IEGT) is proposed in this letter, which has a barrier layer with small windows under the p+ shielding region. The new structure can enhance electron injection through accumulation channel. Thus, an optimized carrier density can be obtained in the emitter side. Compared with conventional SiC insulated gate bipolar transistor and carrier stored trench bipolar transistor, static simulation results show that the static characteristics of the device are improved significantly. The figure of merit ( $V_{\text {BR}}^{2}/R_{\text {on,sp}})$ of AC-IEGT increases by 81.96 % and 17.78 %, respectively. The mix-mode circuit simulation results show that the proposed could be more suitable for ultra-high voltage application.

Analysis of the dynamic avalanche of carrier stored trench bipolar transistor (CSTBT) during clamped inductive turn-off transient

The dynamic avalanche has a huge impact on the switching robustness of carrier stored trench bipolar transistor (CSTBT). The purpose of this work is to investigate the CSTBT’s dynamic avalanche mechanism during clamped inductive turn-off transient. At first, with a Mitsubishi 600V/150A CSTBT and a Infineon 600V/200A field stop insulated gate bipolar transistor (FS-IGBT) utilized, the clamped inductive turn-off characteristics are obtained by double pulse test. The unclamped inductive switching (UIS) test is also utilized to identify the CSTBT’s clamping voltage under dynamic avalanche condition. After the test data analysis, it is found that the CSTBT’s dynamic avalanche is abnormal and can be triggered under much looser condition than the conventional buffer layer IGBT. The comparison between the FS-IGBT and CSTBT’s experimental results implies that the CSTBT’s abnormal dynamic avalanche phenomenon may be induced by the carrier storage (CS) layer. Based on the semiconductor physics, the electric field distribution and dynamic avalanche generation in the depletion region are analyzed. The analysis confirms that the CS layer is the root cause of the CSTBT’s abnormal dynamic avalanche mechanism. Moreover, the CSTBT’s negative gate capacitance effect is also investigated to clarify the underlying mechanism of the gate voltage bump observed in the test. In the end, the mixed-mode numerical simulation is utilized to reproduce the CSTBT’s dynamic avalanche behavior. The simulation results validate the proposed dynamic avalanche mechanisms.

Physics‐based model of LPT CSTBT including MOS‐side two‐dimensional effects

In this study, a physics-based model for light punch through (LPT) carrier stored trench bipolar transistor (CSTBT) is developed. The model is based on the Fourier series solution of ambipolar diffusion equation implemented in MATLAB and Simulink. In the model, the MOS-side two-dimensional (2D) effects resulting from trench gate and carrier storage layer are studied analytically. Assuming high-level injection in LPT buffer layer, the model also describes the carrier transport, redistribution and recombination in the buffer layer in details. The static and transient experiments for a commercial CSTBT are used to validate the presented model. The simulation results are compared with experiment results and good agreement is obtained.

A high performance carrier stored trench bipolar transistor with a field-modified P-base region

A novel high performance carrier stored trench bipolar transistor (CSTBT) with a field- modified P-base region is proposed. Due to the p-pillars inserted into the drift region extending the P-base region to the bottom of the trench gate, the electric field around the trench gate is modified, preventing the CSTBT from breakdown in advance caused by a concentration of the electric field at the edge of the trench gate. The p-pillars under the p-well forming the novel P-base region also provide extra paths for hole transportation. Thus, the switching time is also reduced. Simulation results have shown that the blocking voltage (BV) of the novel CSTBT is almost 430 V higher exhibiting avalanche breakdown properties compared with the conventional CSTBT. Moreover, the turn-off time of the novel structure is 0.3 μs (17%) shorter than the conventional CSTBT with the same gate length.

A novel high-voltage light punch-through carrier stored trench bipolar transistor with buried p-layer

A novel high-voltage light punch-through (LPT) carrier stored trench bipolar transistor (CSTBT) with buried p-layer (BP) is proposed in this paper. Since the negative charges in the BP layer modulate the bulk electric field distribution, the electric field peaks both at the junction of the p base/n-type carrier stored (N-CS) layer and the corners of the trench gates are reduced, and new electric field peaks appear at the junction of the BP layer/N− drift region. As a result, the overall electric field in the N− drift region is enhanced and the proposed structure improves the breakdown voltage (BV) significantly compared with the LPT CSTBT. Furthermore, the proposed structure breaks the limitation of the doping concentration of the N—CS layer (NN—CS) to the BV, and hence a higher NN—CS can be used for the proposed LPT BP-CSTBT structure and a lower on-state voltage drop (Vce(sat)) can be obtained with almost constant BV. The results show that with a BP layer doping concentration of NBP = 7 × 1015 cm−3, a thickness of LBP = 2.5 μm, and a width of WBP = 5 μm, the BV of the proposed LPT BP-CSTBT increases from 1859 V to 1862 V, with NN—CS increasing from 5 × 1015 cm−3 to 2.5 × 1016 cm−3. However, with the same N−-drift region thickness of 150 μm and NN—CS, the BV of the CSTBT decreases from 1598 V to 247 V. Meanwhile, the Vce(sat) of the proposed LPT BP-CSTBT structure decreases from 1.78 V to 1.45 V with NN—CS increasing from 5 × 1015 cm−3 to 2.5 × 1016 cm−3.

High performance CSTBT with p-type buried layer

A novel high performance carrier stored trench bipolar transistor (CSTBT) with a p-type buried layer (PBL-CSTBT) is proposed. The p-type layer of the structure is formed by ion implantation at the bottom of the trench after a partial etching of the P base /N cs layer and the fabrication process is fully compatible with the conventional CSTBT (C-CSTBT) structure. In comparison with the C-CSTBT without a buried layer, the novel structure offers not only high breakdown voltage, but also improved E off -V ce(on) trade-off characteristics.