Carbon Nanotube Transistors Research Articles

Polymer Encapsulants for Threshold Voltage Control in Carbon Nanotube Transistors.

Although carbon nanotube transistors present outstanding performances based on key metrics, large-scale uniformity and repeatability required in printable electronics depend greatly on proper control of the electrostatic environment. Through a survey of polymer dielectric encapsulants compatible with printing processes, a simple correlation is found between the measured interfacial charge density and the onset of conduction in a transistor, providing a rational route to control the electrical characteristics of carbon nanotube transistors. Smooth and continuous balancing of the properties between unipolar p-type and n-type transport is achieved using a molar fraction series of poly(styrene-co-2-vinylpyridine) statistical copolymers combined with an electron-donating molecule. We further demonstrate the easy fabrication of a p-n diode which shows a modest rectification of 8:1.

Real-Time Monitoring of Cellular Cultures with Electrolyte-Gated Carbon Nanotube Transistors.

Cell-based biosensors constitute a fundamental tool in biotechnology, and their relevance has greatly increased in recent years as a result of a surging demand for reduced animal testing and for high-throughput and cost-effective in vitro screening platforms dedicated to environmental and biomedical diagnostics, drug development, and toxicology. In this context, electrochemical/electronic cell-based biosensors represent a promising class of devices that enable long-term and real-time monitoring of cell physiology in a noninvasive and label-free fashion, with a remarkable potential for process automation and parallelization. Common limitations of this class of devices at large include the need for substrate surface modification strategies to ensure cell adhesion and immobilization, limited compatibility with complementary optical cell-probing techniques, and the need for frequency-dependent measurements, which rely on elaborated equivalent electrical circuit models for data analysis and interpretation. We hereby demonstrate the monitoring of cell adhesion and detachment through the time-dependent variations in the quasi-static characteristic current curves of a highly stable electrolyte-gated transistor, based on an optically transparent network of printable polymer-wrapped semiconducting carbon-nanotubes.

Optimization of carbon nano tube field-effect transistors (CNTFET) and compare them to CMOS silicon

In this paper, a brief review of CNT carbon nanotube transistors will be explained and then the optimization methods will be discussed. Details of AC and DC transistor CNFET and Characteristics of CNFET at high temperature also shows that unlike MOSFET flo below the threshold for this type of component temperature is reduced, thus using CNFET at high temperatures can be more quickly and less leakage current is achieved. Processes for the synthesis of CNT are not complete, a subject of controversy in the field fluctuations of density in CNT growth, as well as an analysis of the credit CNFET because sway density of CNT could lead to complete failure CNFET, so to evaluate it, and we later CNFET applications in comparison with CMOS logic circuits using the latest research, we'll CNFET.

Computer runs on carbon nanotubes

Researchers have made the first carbon nanotube computer capable of running simple programs (Nature 2019, DOI: 10.1038/s41586-019-1493-8). The microprocessor integrates more than 14,000 carbon nanotube transistors built with processes used by the electronics industry. “It is a critical first step to move nanotube transistors from research labs into manufacturing plants,” says Qing Cao, a materials scientist at the University of Illinois at Urbana-Champaign who was not involved in the work. Silicon transistors have enabled today’s digital world, but they are now reaching their limits in terms of how small chipmakers can fabricate them. Some researchers believe carbon nanotubes could take electronics onward past silicon. In the past 2 decades, carbon nanotube electronics have progressed from a single transistor to a simple 178-transistor computer reported by a Stanford University team in 2013. Yet a microprocessor that can execute the complex computations necessary to run modern programs requires tens of thousands of

Nanoscale Sensor-Based Tunneling Carbon Nanotube Transistor for Toxic Gases Detection: A First-Principle Study

Carbon nanotube transistor is a spotlight components for toxic gas monitoring. In this regard, we present a new toxic gas molecules sensor base on a single-walled carbon nanotube transistor and use the Poisson and Schrodinger equations in a self-consistent manner and is modeled using non-equilibrium Green’s function. The reaction between gaseous molecules and single-walled carbon nanotubes can harness the charge and potential level inside the channel, which changes the electrical characteristics of the device. Investigations carried out over a 20-nm channel and at a temperature range between 200 and 400 K shows that the conductivity and current–voltage characteristic of the proposed Nano-sensor depend on temperature and gas conditions. According to the simulation results, the decrease in the temperature decreases the OFF-state current of the tunneling carbon nanotube field-effect transistor which leads to a decrease in the leakage current and the band-to-band tunneling. In addition, due to the temperature rise, the sensitivity is increased, and by increasing the dielectric constant of the gas, the on-state current of the device will also increase significantly. The maximum sensitivity for Carbonyl Chloride is 630 (nm/RIU).

43.1: Invited Paper: Large‐area and high‐performance printed carbon nanotube and metal oxide thin film transistors and their applications

With the rapid development of printable electronics, printed thin film transistors (TFTs) have attracted more and more attention due to their wide applications in novel applications including OLED, LED and QLED displays, E‐paper, and printed logic gates and circuits, neuromorphic electronics and wearable electronics.[1‐10] It is well‐known that performance of printed TFTs are largely depended on performance of printable semiconductor inks. Metal oxide and carbon nanotubes have been regarded as one of promising semiconductors for printed TFTs, since they show excellent electrical properties, solubility, high chemical and physical stability[1‐10]. In this work, we reported some new progresses of large‐scale and high‐performance printed carbon nanotube and metal oxide TFTS and their applications, including CMOS‐like gates, hybrid CMOS inverters and neuromorphic electronics. Printed SWCNT TFTs and metal oxide TFTs (64×64 arrays) with excellent electrical properties have been constructed on silicon and glass substrates. Both of them showed good mobility (more than 10 cm2 V‐1 s‐1) and high on/off ratios (107). Hybrid CMOS inverters based on printed metal oxide TFTs and carbon nanotube TFTs exhibited excellent properties with noise margin of 85%, voltage gain of 50, and low power consumption of 0.4 nW (Figure 1). Furthermore, flexible printed CMOS‐like inverters based on printed carbon nanotube TFTs showed with noise margin of 80%, voltage gain of more than 100, and accepted power consumption at low operation voltage (Figure 1).

Modern microprocessor built from complementary carbon nanotube transistors.

Electronics is approaching a major paradigm shift because silicon transistor scaling no longer yieldshistorical energy-efficiency benefits, spurring research towards beyond-silicon nanotechnologies. In particular, carbon nanotube field-effect transistor (CNFET)-based digital circuits promise substantial energy-efficiency benefits, but the inability to perfectly control intrinsic nanoscale defects and variability in carbon nanotubes has precluded the realization of very-large-scaleintegrated systems. Here we overcome these challenges to demonstrate a beyond-silicon microprocessor built entirely from CNFETs. This 16-bit microprocessor is based on the RISC-V instruction set, runs standard 32-bit instructions on 16-bit data and addresses, comprises more than 14,000 complementary metal-oxide-semiconductor CNFETs and is designed and fabricated using industry-standard design flows and processes. We propose a manufacturing methodology for carbon nanotubes, a set of combined processing and design techniques for overcoming nanoscale imperfectionsat macroscopic scales across full wafer substrates. This work experimentally validates a promising path towards practical beyond-silicon electronic systems.

Novel ternary D-Flip-Flap-Flop and counter based on successor and predecessor in nanotechnology

This paper presents a novel design of ternary circuits using carbon nano-tube transistors (CNTFETs). Using multi-valued logic can reduce chip interconnections, which can have a direct effect on chip area and interconnections power consumption. In this paper, at first, a novel design of ternary successor and predecessor is done with one supply voltage and is compared with the previous design based on CNTFETs. It is shown that this new design provides excellent energy efficiency. Furthermore, a novel structure for the D-Flip-Flap-Flop design is proposed by combining the successor and the predecessor; in this D-Flip-Flap-Flop, the second output is the next level of the first output instead of the invert of that, so this D-F.F.F is easily applicable to the counter design. For the first time, two types of ternary synchronous and asynchronous counters are designed based on CNTFETs, which can be extended to the desired bits using the proposed successor and predecessor on the basis of D-Flip-Flap-Flop. Simulation results using HSPICE software and CNT-32 nm model demonstrate that the proposed ternary circuits (successor, predecessor and D-Flip-Flap-Flop) consume significantly lower power, delay and PDP, as compared with the previous works with one supply voltage; Furthermore, the first designs of ternary synchronous and asynchronous counters based on the CNTFETs can function flawlessly with a high performance.

Functionalized Carbon Nanotube Phototransistors with Sub-Femtowatt Sensitivity at Room Temperature

Detecting low intensity light requires photodetectors with high gain. Carbon nanotube (CNT) transistors functionalized with light absorbers have emerged as a promising approach to realize photodetectors that could approach single photon sensitivity at room temperature. Our previous work demonstrated high sensitivity for CNT transistors functionalized with C60, with modeling indicating that electron-donating sensitizers could lead to even better performance. Here we explore this concept and present a P3HT-functionalized CNT phototransistor capable of detecting 500 aW of visible light at room temperature, corresponding to a responsivity of 2e9 A/W (Gain > 4e9). Furthermore, the dynamical processes lead to a significantly improved response time down to the millisecond range. Combined, these factors suggest that functionalized quasi-one-dimensional channels are a promising path for next-generation room temperature photodetectors.

Novel energy-efficient and high-noise margin quaternary circuits in nanoelectronics

Multiple-valued logic (MVL) circuits reduce the complexity of connections, thereby decreasing power consumption and chip area. In the recent years, many studies have been conducted on multiple-valued logic due to the high potentials of carbon nanotube transistors in designing these circuits. (MVL) circuits have less noise margin in comparison to the binary ones because of the adjacency of the levels. In this paper, the quaternary logic gates were designed using a novel structure and two separated paths with diode connection to generate ‘1’ and ‘2’ logic levels. This allowed the better adjustment of parameters, increased noise margin, and reduced the power consumption in the ‘1’ and ‘2’ logic levels. A new method was also developed to design quaternary combinational circuits; this method was implemented in the full adder circuit. The designs were simulated using the HSPICE software and the 32 nm Stanford CNTFET model. The simulation results indicated significant improvements in terms of power consumption, PDP, and noise margins in the new model, as compared to the prior works. The PDP improvements were about 79% and 63% for the proposed buffer and SQI gates, respectively, while it was 70% for the quaternary full adder design, as compared to the best single supply-based work reported so far. Also, noise margins were improved in the proposed buffer, getting close to an ideal noise margin of about Vdd/6.

Channel length scaling of over 100% biaxially stretchable carbon nanotube transistors

Deformable field effect transistors (FETs) are needed for future technologies such as stretchable electronics. We have previously integrated buckled networks of polymer-sorted semiconducting carbon nanotubes and buckled layers of an ion gel dielectric onto elastomeric substrates to create FETs with a channel length of 100 μm that are biaxially stretchable. However, the channel length scaling behavior of this type of FET has not yet been investigated. Of particular concern is the viability of this device architecture when the channel length is reduced below 10 μm, approaching the characteristic buckling length-scale. Here, we fabricate and test buckled nanotube FETs with channel lengths of 8, 17, and 31 μm. We find that the buckling length-scale decreases as the channel length is reduced and that devices at all channel lengths are viable, demonstrating a field-effect mobility of >5 cm2 V−1 s−1 and an on/off ratio of >104, with stability up to 100% biaxial elongation without degradation of performance. A biaxially stretchable inverter is also demonstrated. These findings are important because smaller and higher conductivity FETs that are deformable are needed for next-generation technologies such as stretchable, high-resolution displays and sensors.

Graphene and Carbon Nanotube Heterojunction Transistors with Individual Gate Control.

Heterogeneously integrated nanomaterial devices show interesting characteristics for transistors and sensors due to their band diagram or steep material junctions. If these junctions and band alignments can be tuned by an electrical input bias, the device platform not only could be expanded but also could be used to explore fundamental characteristics. However, most reports on hetero-nanomaterial junctions use a global back-gate voltage, which makes it difficult to control band alignment at an interface. To explore device junctions, this study reports a laterally integrated heterojunction of graphene and a carbon nanotube (CNT) network film with individual gate electrodes to tune the band alignment corresponding to the Fermi level shift of graphene in contact with the semiconducting CNT network film. By developing the fabrication process, multiple gate structures are designed to apply a gate bias to CNTs and graphene separately. The threshold voltage shift of the CNT transistor depends on the gate voltage of graphene. Based on the thermionic emission theory, the barrier height between graphene and CNTs for both the conduction and valence band sides varies from 70 to 85 meV, with a linear change as a function of the applied gate voltage to graphene. Although the current Fermi level shift is small, this device platform may realize the exploration of fundamental properties and device concepts.

Polarity tuning of carbon nanotube transistors by chemical doping for printed flexible complementary metal-oxide semiconductor (CMOS)-like inverters

Low operation voltages and strong noise immunity are crucial for low-power applications in portable or remote devices. In this work, we present a simple and effective approach to achieve low-voltage and high noise margin complementary metal-oxide semiconductor (CMOS)-like inverters using printed symmetric ambipolar single-walled carbon nanotubes (SWCNT) TFTs on flexible substrates. An ion gel dielectric material with high capacitance is used to achieve small hysteresis and small subthreshold swing at low operation voltages. The printed SWCNT TFTs exhibit a p-type depletion-mode behavior and can be converted into symmetric ambipolar TFTs by chemical doping of triethanolamine into the ion gel inks. The CMOS-like inverters consisting of two ambipolar TFTs exhibit a large noise margin of 72% and 83% at 1/2 VDD = 0.5 V, voltage gain as high as 23 and power consumption of 0.9 μW at VDD = 0.5 V. To our knowledge, they are the best reported values of printed CMOS-like inverter using ion gels as dielectric material at a VDD of 0.5 V. Additionally, the flexible printed CMOS-like inverters consisting of a p-type and an ambipolar TFTs also work well and showed full rail-to-rail output voltage swing and low power consumption (0.3 μW at VDD = 0.75 V).

Improved Device Performance of Solution-Processed Single-Wall Carbon Nanotube Transistors by a Patterning Technique Using a Selective Surface Treatment.

During the fabrication processes for single-wall carbon nanotube thin-film transistors (SWCNT-TFTs), the impurities of organic residues such as photoresist and developer can be induced, which affects the charge transport. As a result, solution-processed SWCNT-TFTs exhibit poor and non-uniform device performance regardless of the intrinsic electrical characteristics. Here, we demonstrate a patterning technique using a selective surface treatment with solution-processed hydrophobic fluorocarbon copolymer in SWCNT-TFTs. By using the difference of wettability in a selective area, a channel region in SWCNT-TFTs can be patterned without the conventional photolithography and etching process. Furthermore, the optimized surface treatment results in denser random networks of SWCNTs in the channel patterned by such technique, compared to the dropcasted SWCNT. The statistical results of the key device metrics such as mobility and threshold voltage extracted from 30 SWCNT-TFTs conclusively prove the improved device performance of SWCNT-TFTs fabricated by such pattering technique. We believe that this work can provide a promising route to stimulate the process innovation of fabrication for high performance solution-processed electronics based on SWCNT random networks.

Electronic Stability of Carbon Nanotube Transistors Under Long-Term Bias Stress.

Thousands of reports have demonstrated the exceptional performance of sensors based on carbon nanotube (CNT) transistors, with promises of transformative impact. Yet, the effect of long-term bias stress on individual CNTs, critical for most sensing applications, has remained uncertain. Here, we report bias ranges under which CNT transistors can operate continuously for months or more without degradation. Using a custom characterization system, the impacts of defect formation and charge traps on the stability of CNT-based sensors under extended bias are determined. In addition to breakdown, which is well-known, we identify three additional operational modes: full stability, slow decay, and fast decay. We identify a current drift behavior that reduces dynamic range by over four orders of magnitude but is avoidable with appropriate sensing modalities. Identification of these stable operation modes and limits for nanotube-based sensors addresses concerns surrounding their development for a myriad of sensing applications.

Low-Temperature Side Contact to Carbon Nanotube Transistors: Resistance Distributions Down to 10 nm Contact Length

Carbon nanotube field-effect transistors (CNFETs) promise to improve the energy efficiency, speed, and transistor density of very large scale integration circuits owing to the intrinsic thin channel body and excellent charge transport properties of carbon nanotubes. Low-temperature fabrication (e.g., <400 °C) is a key enabler for the monolithic three-dimensional (3D) integration of CNFET digital logic into a device technology platform that overcomes memory bandwidth bottlenecks for data-abundant applications such as big-data analytics and machine learning. However, high contact resistance for short CNFET contacts has been a major roadblock to establishing CNFETs as a viable technology because the contact resistance, in series with the channel resistance, reduces the on-state current of CNFETs. Additionally, the variation in contact resistance remains unstudied for short contacts and will further degrade the energy efficiency and speed of CNFET circuits. In this work, we investigate by experiments the contact resistance and statistical variation of room-temperature fabricated CNFET contacts down to 10 nm contact lengths. These CNFET contacts are ∼15 nm shorter than the state-of-the-art Si CMOS "7 nm node" contact length, allowing for multiple generations of future scaling of the transistor-contacted gate pitch. For the 10 nm contacts, we report contact resistance values down to 6.5 kΩ per source/drain contact for a single carbon nanotube (CNT) with a median contact resistance of 18.2 kΩ. The 10 nm contacts reduce the CNFET current by as little as 13% at VDS = 0.7 V compared with the best reported 200 nm contacts to date, corroborated by results in this work. Our analysis of RC from 232 single-CNT CNFETs between the long-contact (e.g., 200 nm) and short-contact (e.g., 10 nm) regimes quantifies the resistance variation and projects the impact on CNFET current variability versus the number of CNT in the transistor. The resistance distribution reveals contact-length-dependent RC variations become significant below 20 nm contact length. However, a larger source of CNFET resistance variation is apparent at all contact lengths used in this work. To further investigate the origins of this contact-length-independent resistance variation, we analyze the variation of RC in arrays of identical CNFETs along a single CNT of constant diameter and observe the random occurrence of high RC, even on correlated CNFETs.

A Variation-Aware Ternary Spin-Hall Assisted STT-RAM Based on Hybrid MTJ/GAA-CNTFET Logic

Magnetic random access memory is a promising solution to keep up with the trend of memory sizing. On the other hand, the multiple-valued logic has been considered as a promising solution for some important challenges of the binary integrated circuits. In this paper, a novel ternary magnetic RAM (TMRAM) based on sub-10 nm gate-all-around carbon nanotube transistor (GAA-CNTFET) is proposed. The proposed TMRAM cell utilizes magnetic tunnel junction (MTJs) to provide non-volatility and spin-hall assisted spin-transfer torque method to reduce the write energy. Moreover, GAA-CNTFETs provide ternary operation and enhance the cell performance and efficiency. The read and write circuitry of the proposed magnetic memory cell contains no sense amplifier and bistable feedback, which makes it invulnerable to radiations effects. The efficiency of the proposed TMRAM cell becomes more apparent in the TMRAM block structures due to the reduction in the number of transistors. The proposed approach is simulated using HSPICE and its performance is evaluated in presence of variations in the critical process parameters of MTJ and GAA-CNTFET by Monte-Carlo simulations. The results indicate the correct and efficient operation of the proposed design even in the presence of different process variations.

Direct Measurement of π Coupling at the Single-Molecule Level using a Carbon Nanotube Force Sensor.

We report a carbon nanotube (CNT) force sensor that combines a suspended CNT transistor with dual-trap optical tweezers to explore the interactions between two individual molecules in the near-equilibrium regime with sub-piconewton resolution. The directly measured equilibrium force (1.2 ± 0.5 pN) is likely related to the binding force between a CNT and a single DNA base, where two aromatic rings spontaneously attract to each other due to the noncovalent forces between them. On the basis of our force measurements, the binding free energy per base is calculated (∼0.34 eV), which is in good agreement with theoretical simulations. Moreover, three-dimensional scanning photocurrent microscopy enables us to simultaneously monitor the morphology changes of the CNT, leading to a comprehensive reconstruction of the CNT-DNA binding dynamics. These experimental results shed light on the fundamental understanding of the mechanical coupling between CNTs and DNA molecules and, more importantly, provide a new platform for direct observation of intermolecular interfaces at the single-molecule level.

High-Quality Solution-Processed Metal-Oxide Gate Dielectrics Realized With a Photo-Activated Metal-Oxide Nanocluster Precursor

High-quality solution-derived amorphous alumina ( ${a}$ -Al2O3) dielectric has been achieved with [Al $_{\textsf {13}}{(}\mu _{\textsf {3}}$ -OH ${)}_{\textsf {6}}{(}\mu $ -OH)18 (H2O)24](NO3)15(Al-13 nanocluster) as a precursor and a local structure-controllable activation process via deep-UV-induced photochemical activation. The synergetic combination of an Al-13 nanocluster precursor and high-energetic photochemical activation enables the formation of highly dense ${a}$ -Al2O3 thin films via an efficient dissociation and rearrangement of the nanocluster skeleton. The electrical characteristics of the nanocluster-based ${a}$ -Al2O3 thin films were investigated in terms of their operative electronic conduction mechanism by comparing conventional nitrate-based and vacuum-deposited films. From these results, it was found that the leakage current density of solution-processed ${a}$ -Al2O3 layers is largely affected by their precursor structures. Finally, to demonstrate the versatility of the high-quality nanocluster-based ${a}$ -Al2O3 dielectrics, carbon nanotube and metal-oxide thin-film transistors were fabricated on low thermal budget stretchable and rigid substrates, respectively.

Fully Printed Flexible Dual-Gate Carbon Nanotube Thin-Film Transistors with Tunable Ambipolar Characteristics for Complementary Logic Circuits

Semiconducting single-wall carbon nanotubes (sSWCNTs) have been widely used as the channel material for high-performance printed flexible thin-film transistors (TFTs). Due to the absorption of moisture and oxygen in air, the printed sSWCNT TFTs generally exhibit p-type characteristics only. In this paper, we report fully printed dual-gate sSWCNT TFTs that exhibit almost symmetric ambipolar characteristics. With the applied control gate voltage varying from -60 to +60 V, a threshold voltage tuning range of 27 V is achieved, allowing the device to be effectively tuned into either predominantly p-type or predominantly n-type. The tunable ambipolar characteristics are found to be very stable over a long period of time (4 months). By integrating two printed dual-gate TFTs biased with different control gate voltages, a complementary metal oxide semiconductor inverter with close to rail-to-rail output voltage swing is demonstrated. The use of a dual-gate structure for achieving n-type printed carbon nanotube TFTs is much more controllable and repeatable compared to other methods such as chemical doping. Our work shows the feasibility of implementing more sophisticated complementary logic circuits using printed flexible carbon nanotube transistors.