Carbon Nanotube Transistors Research Articles

Design and Implementation of Carbon Nano-tube based Full Adder at 32nm Technology for High Speed and Power Efficient Arithmetic Applications

Due to physical, material, technological, power-thermal and economical difficulties, scaling of CMOS transistors will stop very soon. Due to efficiency of power and speed compared to CMOS transistors, Carbon Nano-tube transistors are best suitable element to design logic circuits. So, CNTFETS have been utilized in designing of proposed full adder (FA) and 4-bit ripple carry adder (RCA) in this paper. Proposed FA and RCA have been compared to rival designs on bases of power, speed and power-delay-product (PDP). FA and RCA circuits have been analysed with the variation of temperature from 0°C to 100°C while the variation of supply voltages is from 0.7V to 1.3V. For all temperatures and all supply voltages, proposed FA and proposed RCA have the least power consumption, shortest delay and lowest PDP. SPICE has been utilized for simulating FAs and RCAs in 32 nm process node. Even though the fabrication is complicated than CMOS counterparts but simulation results confirm usefulness of proposed FA and RCA for high speed and power efficient arithmetic applications.

Ionic dielectrics for fully printed carbon nanotube transistors: impact of composition and induced stresses.

Printed carbon nanotube thin-film transistors (CNT-TFTs) are candidates for flexible electronics with printability on a wide range of substrates. Among the layers comprising a CNT-TFT, the gate dielectric has proven most difficult to additively print owing to challenges in film uniformity, thickness, and post-processing requirements. Printed ionic dielectrics show promise for addressing these issues and yielding devices that operate at low voltages thanks to their high-capacitance electric double layers. However, the printing of ionic dielectrics in their various compositions is not well understood, nor is the impact of certain stresses on these materials. In this work, we studied three compositionally distinct ionic dielectrics in fully printed CNT-TFTs: the polar-fluorinated polymer elastomer PVDF-HFP; an ion gel consisting of triblock polymer PS-PMMA-PS and ionic liquid EMIM-TFSI; and crystalline nanocellulose (CNC) with a salt concentration of 0.05%. Although ion gel has been thoroughly studied, e-PVDF-HFP and CNC printing are relatively new and this study provides insights into their ink formulation, print processing, and performance as gate dielectrics. Using a consistent aerosol jet printing approach, each ionic dielectric was printed into similar CNT-TFTs, allowing for direct comparison through extensive characterization, including mechanical and electrical stress tests. The ionic dielectrics were found to have distinct operational dependencies based on their compositional and ionic attributes. Overall, the results reveal a number of trade-offs that must be managed when selecting a printable ionic dielectric, with CNC showing the strongest performance for low-voltage operation but the ion gel and elastomer exhibiting better stability under bias and mechanical stresses.

An SRAM Compiler for Monolithic-3-D Integrated Circuit With Carbon Nanotube Transistors

This article presents monolithic-3-D (M3D) SRAM arrays using multiple tiers of carbon nanotube (CNT) transistors. The compiler automatically generates single-tier 2-D SRAM subarrays and multitier 3-D SRAM subarrays with different tiers for cells and peripheral logic. Moreover, the compiler can integrate multiple subarrays of different dimensions to generate larger capacity SRAM arrays. The compiler is demonstrated in a commercial-grade M3D process design kit (PDK) with two tiers of carbon nanotube transistors (CNFETs). Simulations show that the M3D CNT SRAM design can improve the properties of memory compared to the 2-D CNT SRAM design. In a 32-kB memory implementation, the M3D design can reduce footprint, latency, and energy by 33%, 10%, and 19%, respectively. The compiler is used to show the feasibility of fine-grain logic and SRAM stacking in M3D technology.

Tetrahedral DNA nanostructure based biosensor for high-performance detection of circulating tumor DNA using all-carbon nanotube transistor

Adopting carbon nanotube (CNT) transistors as biosensors has been developed as a promising method for cancer biomarker detection, which has shown superior sensitivity and selectivity. However, the detection of circulating tumor DNA (ctDNA) by the CNT transistor based biosensors is still a challenge and no work has been reported. Here, direct label-free DNA detection of AKT2 gene related to triple-negative breast cancer by all-CNT thin-film transistor (TFT) biosensors incorporated with tetrahedral DNA nanostructures (TDNs) is proposed and achieved for the first time. The adoption of TDNs enables improved biosensor response for at least 35% and even as high as 98% as compared with single-stranded DNA (ssDNA) probes owing to the enhanced DNA hybridization efficiency. Influence of the TDNs’ linker length on the biosensor performance is important and has been investigated. Concentration-dependent DNA detection is achieved by the all-CNT TFT biosensors with a broad linear detection range of six orders of magnitude and a theoretical limit of detection (LOD) of 2 fM. In addition, the all-CNT TFT biosensors exhibit favorable selectivity and repeatability. The platform of all-CNT TFT biosensors incorporated with TDNs has great potential for multiplexed detection of various cancer biomarkers, providing a simple yet high performance universal strategy for low-cost clinical applications.

A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube Process

We present a ReRAM memory compiler for monolithic 3D (M3D) integrated circuits (IC). We develop ReRAM architectures for M3D ICs using 1T-1R bit cells and single and multiple tiers of transistors for access and peripheral circuits. The compiler includes an automated flow for generation of subarrays of different dimensions and larger arrays of a target capacity by integrating multiple subarrays. The compiler is demonstrated using an M3D process design kit (PDK) based on a Carbon Nanotube Transistor technology. The PDK includes multiple layers of transistors and back-end-of-the-line integrated ReRAM. Simulations show the compiled ReRAM macros with multiple tiers of transistors reduces footprint and improves performance over the macros with single-tier transistors. The compiler creates layout views that are exported into library exchange format or graphic data system for full-array assembly and schematic/symbol views to extract per-bit read/write energy and read latency. Comparison of the proposed M3D subarray architectures with baseline 2D subarrays, generated with a custom-designed set of bit cells and peripherals, demonstrate up to 48% area reduction and 13% latency improvement.

Reconfigurable Carbon Nanotube Barristor

AbstractAs the semiconductor industry enters the post‐Moore era, reconfigurability on the device level, that incorporates multifunction in a device unit to realize more complex systems with more compact logic gates, is a promising methodology to extend the development of integrated circuit industry. Here, a reconfigurable carbon nanotube (CNT) barristor is developed on the basis of a Schottky barrier (SB) CNT transistor. The device shows a significant rectifying characteristic and can be reconfigured to a forward rectifying mode or a backward rectifying mode by applying an appropriate gate voltage. The reconfigurability originates from the ambipolar characteristics of the CNT channel, and the rectification behaviors can be attributed to the drain‐induced self‐gating effect. Additional experiments reveal that it is the interfacial charge redistribution that plays the role of an additional gate on the SB near the drain. A gate‐controllable half‐wave rectifier has been fabricated by using the reconfigurable CNT barristor. The CNT barristor brings new functions to CNT electronic devices and also opens up a new methodology for future reconfigurable device design.

Single-Walled Carbon Nanotube-Based Field-Effect Transistors Functionalized with Odorant Receptors for Biosensing Applications

Bioelectronic detection with functionalized carbon nanotube transistor devices, known as CNT-FET, offers signal levels comparable with voltage clamp, multiplexing potential similar to microarray and amenability for miniaturization. The feasibility of CNT-FET biosensors was demonstrated in the detection of nucleic acids and various protein biomarkers and they are considered the next generation bioelectronic-based biosensors. Detection of volatiles and specifically volatile organic compounds (VOC) with CNT-FETs is less common, let alone devices that were biofunctionalized for specificity. The detection of VOCs has been demonstrated in a wide range of applications, with early reports focusing on environmental exogenous VOCs due to their adverse effects on human health; bacterial VOC signatures used as disease biomarkers, etc.. Methods that rely on separation techniques coupled with mass spectrometry are considered the ’gold standard’ in this field. These methods require expensive equipment, labor-intensive preparation steps and trained personnel, and are not suitable for field use. A method enabling high-throughput screening of VOCs such as insect behavior-modifying drugs, disease biomarkers, etc. is highly desirable.Bioelectronic sensors are ideally suited for the detection of pathogenic volatile markers (VOC). In order to confer ultrahigh specificity on an electronic sensor, a bio-recognition element needs to be incorporated with the transducer. In the case of VOC sensing, one such promising element is the natural insect odorant receptor (OR). Insect OR exhibit remarkable sensitivities and the ability to selectively detect a vast number of VOCs. These heteromeric transmembrane proteins transduce signals by acting as ligand-gated ion channels. We have recently developed OR-functionalized carbon nanotube field-effect transistor (FET) devices. These FET devices integrate an isolated single-walled carbon nanotube (SWCNT) as the conducting channel material.Indole and skatoles are microbial volatile organic compounds (VOCs). Depending on their concentrations, these odorants indicate environmental contaminants, metabolic disorders, food spoilage, human presence and malodorants.The indolergic receptor (IndolOR) named OR9 is the most sensitive odorant receptor discovered so far. We have developed a bioelectronic assay platform in the form of OR9-functionalized CNT-FET arrays. Our unique functionalization method is based on directing the attachment of a native OR9-containing nanovesicles (which we have exogenously expressed and functionally characterized) to the CNT-FET point defect. Target binding-induced ionic current and conformational changes of OR9 affect an electric field that modulates the device conductance. Figure 1

Applications of Carbon Nanotubes in the Internet of Things Era

HighlightsThe Internet of Things era related electronics were updated based on carbon nanotube transistors, radiofrequency circuits and energy storage devices.The applications in healthcare and biomedical devices were discussed including sensory, data processors and actuators.The fabrication of wafer-scale carbon nanotubes has been introduced as well as the machine learning strategy for prediction of optimal synthesis parameters.

Recent advances in printable carbon nanotube transistors for large-area active matrices

Active-matrices serve as the backplane circuitry for large-area display technologies and distributed sensors. Recently, there has been significant interest in developing flexible, additively manufactured active matrices for the burgeoning flexible electronics industry. Carbon nanotubes (CNTs) are prime candidate materials for semiconducting elements of transistors due to their solution processability, carrier mobility, and mechanical flexibility. There have been many recent accomplishments in the development of CNT inks and in their deposition via printing that enable their use in thin-film transistors (TFTs), and their appropriate performance make them suitable for use in large-area active matrices. In this review, we provide an overview of the field, with a specific focus on recent advancements in CNT sorting, ink preparation, and printing techniques. We also provide a benchmarking study of printed CNT devices presented in literature after 2017. Next, we discuss printable CNT-TFTs used for active-matrix applications. Finally, we provide a concluding perspective on the outlook and challenges for printed CNT-TFT active matrices.

Can Carbon Nanotube Transistors Be Scaled Down to the Sub-5 nm Gate Length?

Single-walled carbon nanotubes (CNTs) have been considered as a promising semiconductor to construct transistors and integrated circuits in the future owing to their ultrathin channel thickness and ultrahigh injection velocity. Although a 5 nm gate-length CNT field-effect transistor (FET) has already been experimentally fabricated and demonstrates excellent device performance, the potential or constraint factors on performance have not been explored or revealed. Based on the benchmark of the device performance between the experimental and simulated 5 nm gate-length CNT FETs, we use the first-principles quantum transport approach to explore the performance limit of CNT FETs based on the gate-all-around (GAA) device geometry for the first time. It is found that the GAA CNT FETs can fulfill the ITRS 2028 high-performance target in the 2 nm gate-length node in terms of the on-state current, delay time, and power consumption. We also find that the energy-delay product of the CNT FETs is superior to those of the high-performance 2D materials and Si Fin FETs at the sub-5 nm gate length due to its unique electrical property. Though theoretically the gate length of CNT FETs can be potentially scaled to 2 nm, considering the tradeoff between the performance and power consumption, 5 nm is the ultimate scaled limit.

Highly Temperature‐Stable Carbon Nanotube Transistors and Gigahertz Integrated Circuits for Cryogenic Electronics

AbstractCryogenic electronics are attracting more and more attentions owing to the rising of space exploration and quantum computing, in which low‐temperature stable operation is even more concerned than performance of the integrated circuits (ICs). As a promising semiconducting material, carbon nanotube (CNT) has been extensively explored on its low‐temperature transport characteristics, but the cryogenic electronics application of CNT transistors and ICs has seldom been demonstrated. In this work, the low‐temperature operation of field‐effect transistors (FETs) and ICs built on solution‐derived high semiconducting purity randomly oriented CNT film is investigated. The randomly oriented CNT FETs exhibit much higher temperature stability than the individual CNT based FETs and Si transistors from room temperature to liquid nitrogen temperature, and then the ICs constructed by the CNT film FETs present excellent temperature‐stability. Specifically, the fabricated five‐stage ring oscillators (ROs) exhibit oscillation frequency up to 1.5 GHz with the performance change less than 0.5% at the temperature ranging from 300 to 80 K. The work reveals the great potential of high‐performance transistors and ICs built on randomly oriented CNT films in cryogenic electronics applications.

Prospects for single-molecule electrostatic detection in molecular motor gliding motility assays

Molecular motor gliding motility assays based on myosin/actin or kinesin/microtubules are of interest for nanotechnology applications ranging from cargo-trafficking in lab-on-a-chip devices to novel biocomputation strategies. Prototype systems are typically monitored by expensive and bulky fluorescence microscopy systems. The development of integrated, direct electric detection of single filaments would strongly benefit applications and scale-up. We present estimates for the viability of such a detector by calculating the electrostatic potential change generated at a carbon nanotube transistor by a motile actin filament or microtubule under realistic gliding assay conditions. We combine this with detection limits based on previous state-of-the-art experiments using carbon nanotube transistors to detect catalysis by a bound lysozyme molecule and melting of a bound short-strand DNA molecule. Our results show that detection should be possible for both actin and microtubules using existing low ionic strength buffers given good device design, e.g., by raising the transistor slightly above the guiding channel floor. We perform studies as a function of buffer ionic strength, height of the transistor above the guiding channel floor, presence/absence of the casein surface passivation layer for microtubule assays and the linear charge density of the actin filaments/microtubules. We show that detection of microtubules is a more likely prospect given their smaller height of travel above the surface, higher negative charge density and the casein passivation, and may possibly be achieved with the nanoscale transistor sitting directly on the guiding channel floor.

PN junction and band to band tunneling in carbon nanotube transistors at room temperature

We demonstrate band to band tunneling (BTBT) in a carbon nanotube (CNT) field effect transistor. We employ local electrostatic doping assisted by charged traps within the oxide to produce an intramolecular PN junction along the CNT. These characteristics apply for both metallic (m-CNTs) and semiconducting (SC-CNTs) CNTs. For m-CNTs we present a hysteretic transfer characteristic which originates from local electrostatic doping in the middle segment of the CNT. This controlled doping is reversible and results in formation and destruction of a PN junction along the CNT channel. For SC-CNTs we observe BTBT, and analysis based on the WKB approximation reveals a very narrow depletion region and high transmission probability at the optimal energy bands overlap. These results may assist in developing a non-volatile one-dimensional PN junction memory cell and designing a tunneling based field effect transistor.

Ambipolar carbon nanotube transistors with hybrid nanodielectric for low-voltage CMOS-like electronics

The proliferation of place-and-forget devices driven by the exponentially-growing Internet of Things industry has created a demand for low-voltage thin-film transistor (TFT) electronics based on solution-processible semiconductors. Amongst solution-processible technologies, TFTs based on semiconducting single-walled carbon nanotubes (sc-SWCNTs) are a promising candidate owing to their comparatively high current driving capability in their above-threshold region at low voltages, which is desirable for applications with constraints on supply voltage and switching speed. Low-voltage above-threshold operation in sc-SWCNTs is customarily achieved by using high-capacitance-density gate dielectrics such as metal-oxides fabricated via atomic layer deposition (ALD) and ion-gels. These are unattractive, as ALD requires complex-processing or exotic precursors, while ion-gels lead to slower devices with poor stability. This work demonstrates the fabrication of low-voltage above-threshold sc-SWCNTs TFTs based on a high-capacitance-density hybrid nanodielectric, which is composed of a readily-made AlO x nanolayer and a solution-processed self-assembled monolayer (SAM). The resultant TFTs can withstand a gate-channel voltage of 1–2 V, which ensures their above-threshold operation with balanced ambipolar behavior and electron/hole mobilities of 7 cm2 V−1 s−1. Key to achieving balanced ambipolarity is the mitigation of environmental factors via the encapsulation of the devices with an optimized spin-on polymer coating, which preserves the inherent properties of the sc-SWCNTs. Such balanced ambipolarity enables the direct implementation of CMOS-like circuit configurations without the use of additional dopants, semiconductors or source/drain electrode metals. The resultant CMOS-like inverters operate in the above-threshold region with supply voltages in the 1–2 V range, and have positive noise margins, gain values surpassing 80 V/V, and a bandwidth exceeding 100 kHz. This reinforces SAM-based nanodielectrics as an attractive route to easy-to-fabricate sc-SWCNT TFTs that can operate in the above-threshold region and that can meet the demand for low-voltage TFT electronics requiring moderate speeds and higher driving currents for wearables and sensing applications.

Low-power high-speed phase frequency detector based on carbon nano-tube field effect transistors

A phase frequency detector (PFD) with a very low dead zone is proposed which is based on a configuration adaptable to both CMOS or carbon nano-tube transistors (CNTFETs). In the first step the proposed configuration is designed using CMOS transistors, and then CNTFETs are substituted to improve the speed and reduce the propagation delay. The proposed PFD in addition to very low dead zone, has low power consumption and high frequency range of operation, which are achieved as a result of the elimination of the reset path. The simulation results based on 32 nm technology for CNTFET and 180 nm technology for CMOS, illustrate that CNTFET-based proposed circuit dissipates 2 µW and has frequency of operation up to 30 GHz, and the dead zone equal to 1 ps. Compared to the conventional PFD based on CMOS technology, its dead zone and power consumption are lower. In addition, the effects of blocks’ parameters including the phase detector, which affect the operation of the phase locked loop, or delay locked loop, are systematically analyzed.

A novel model of binary and ternary Schmitt triggers based on multi-threshold voltage in nanoelectronics

In the recent years, the scaling of the CMOS technology, resulting in further reduction of dimensions, has become a severe challenge. The technology of carbon nanotube transistor (CNFET) is one of the most promising ones to replace CMOS. It is, in fact, expected to be commercialized in the coming years. In this paper, as the first step, a binary Schmitt trigger (Binary-ST) is proposed, in which setting the upper trigger point (UTP) and lower trigger point (LTP) is possible separately by only changing the diameter of nanotubes for the two CNFETs used in the input. On the basis of this feature, two Schmitt triggers are designed: Positive Schmitt trigger (POS-ST), in which UTP and LTP are greater than VDD/2, and the negative Schmitt trigger (NEG-ST), in which UTP and LTP are less than VDD/2. In the second step, due to combining these two binary Schmitt triggers, the first ternary Schmitt trigger(Ternary-ST) in nanoelectronics is introduced. Simulation results using Stanford CNFET model at 32 nm technology suggest that in the proposed binary Schmitt trigger, in addition to simply adjusting the UTP and LTP and high input resistance, PDP and EDP were improved about 18% and 25% respectively, as compared to the best work with CNFET. Also, the first proposed ternary Schmitt trigger in nanoelectronics displayed a correct operation and proper performance. The proposed circuits were evaluated under temperature, load and process variation, thus confirming the proper stability and ternary Schmitt trigger performance is insensitive against PVT variations.

CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic

This paper presents a ternary half adder and a 1-trit multiplier using carbon nanotube transistors. The proposed circuits are designed using pass transistor logic and dynamic logic. Ternary logic uses less connections than binary logic, and less voltage changes are required for the same amount of data transmission. Carbon nanotube transistors have advantages over MOSFETs, such as the same mobility for electrons and holes, the ability to adjust the threshold voltage by changing the nanotube diameter, and less leakage power. The proposed half adder has lower power consumption, delay, and fewer transistors compared to recent ternary half adders that use similar design methods. The proposed 1-trit multiplier also has a lower delay than other designs. Moreover, these advantages are achieved over a wide supply voltage range, operating temperatures, and output loads. The design is also more robust to process variations than the nearest design in terms of PDP.

Carbon nanotube transistor technology for More-Moore scaling

Scaling of silicon field-effect transistors has fueled the exponential development of microelectronics in the past 60 years, but is now close to its physical limits with the critical dimensions of state-of-the-art silicon devices approaching the sub-10 nm regime. Carbon nanotubes have been suggested to hold great promise of replacing the central role of silicon in the next-generation logic switches with their unique geometrical and electrical properties. In this article, I firstly examine the scaling advantages of carbon nanotubes compared to silicon from technology-development perspective, and then review the latest progress on addressing the manufacturability issues for scaled carbon-nanotube transistors, from materials to device-integration levels. Finally, the possible pathways for nanotube transistors to transition into commercial applications are discussed.

Scalable and selective N-type conversion for carbon nanotube transistors via patternable polyvinyl alcohol stacked with hydrophobic layers and their application to complementary logic circuits

Herein, this study reports scalable and selective n-type conversion (N/C) approach for single walled carbon nanotube (SWNT) transistors with high reproducibility by using novel control of hydroxyl groups through condensation on the surface of SWNTs, via the patternable cross-linked polyvinyl alcohol (C-PVA), followed by encapsulation of photo-definable hydrophobic polymer (~SU8). Moreover, N/C process capability is statistically evaluated in terms of selective doping, process yield, and statistical variation in electrical parameters, and as practical validation, complementary inverters, NOR and NAND logic gates are fully demonstrated. As one of key findings, it is elucidated that N/C uniformity and its underlying physics, supported by Fourier-transform infrared spectroscopy (FTIR) and Raman analysis, are highly correlated with ambient condition, C-PVA thickness, and encapsulation. More practically, reproducible field effect mobility for n-type (or p-type) SWNT TFTs after (or before) N/C are achieved at ~ 3.65 ± 1.30 (or 8.76 ± 2.16) cm2 V−1 s−1, with magnificent process yield (~100%) and reasonable mobility reduction, which is on par with the previous report. Hence, all demonstration and their analyses suggest that this scalable N/C scheme for SWNT TFTs can be one of core technologies for the next generation semiconductor-based devices and their envisioned application.

Reactivity of an air-stable dihydrobenzoimidazole n-dopant with organic semiconductor molecules

Summary 1,3-Dimethyl-2-(4-(dimethylamino)phenyl)-2,4-dihydro-1H-benzoimidazole, N-DMBI-H, is widely used as an air-stable n-dopant for organic semiconductors. Here, its reactivity is investigated with a variety of imide- and amide-containing semiconductor molecules that have reduction potentials in the range −0.54 to −1.10 V versus ferrocene. Reaction rates correlate poorly with these potentials. The more reactive of the imides form the corresponding radical anions cleanly, but kinetic isotope studies using N-DMBI-D indicate that the reaction proceeds via an initial hydride- or hydrogen-transfer step. For an amide- and ester-rigidified bis(styryl)benzene derivative the hydride-reduced product is stable under an inert atmosphere and can be observed directly; the radical anion can only be obtained in sub-stoichiometric yield and under certain reaction conditions. On the other hand, (N-DMBI)2 rapidly reduces all the imides and amides examined to the corresponding radical anions. The implications of these findings for dopant selection and use are discussed.