Carbon Nanotube Field-effect Transistors Research Articles

Orientation-Guided Immobilization of Probe DNA on swCNT-FET for Enhancing Sensitivity of EcoRV Detection.

We present a novel approach that integrates electrical measurements with molecular dynamics (MD) simulations to assess the activity of type-II restriction endonucleases, specifically EcoRV. Our approach employs a single-walled carbon nanotube field-effect transistor (swCNT-FET) functionalized with the EcoRV substrate DNA, enabling the detection of enzymatic cleavage events. Notably, we leveraged the methylene blue (MB) tag as an "orientation guide" to immobilize the EcoRV substrate DNA in a specific direction, thereby enhancing the proximity of the DNA cleavage reaction to the swCNT surface and consequently improving the sensitivity in EcoRV detection. We conducted computational modeling to compare the conformations and electrostatic potential (ESP) of MB-tagged DNA with its MB-free counterpart, providing strong support for our electrical measurements. Both conformational and ESP simulations exhibited robust agreement with our experimental data. The inhibitory efficacy of the EcoRV inhibitor aurintricarboxylic acid (ATA) was also evaluated, and the selectivity of the sensing device was examined.

Energy-Efficient High-Speed dynamic logic-based One-Trit multiplier in CNTFET technology

The appeal of portable electronics, embedded systems, and other smart devices has been steadily growing over time. The multi-valued logic (MVL) was primarily introduced to handle the interconnect issues in binary logic. The use of ternary logic reduces the circuit complexity, power consumption in interconnects, and total chip area. The carbon nanotube field-effect transistor (CNTFET) offers some significant features like low leakage power, equal hole and electron mobility, and modulation in threshold voltage by adjusting the diameter of the carbon nanotube (CNT). In this paper, a clocked dynamic and pass transistor logic-based ternary 1-trit multiplier circuit with only 28 transistors has been proposed. The proposed logic avoids the conventional approach of using logic gates, encoder/decoder, and multiplexers, which reduces the total device count to implement the multiplier. The reduced transistor count offers a reduction in power consumption, delay, power-delay-product (PDP), and energy-delay-product (EDP) in comparison to other state-of-the-art designs. Stanford 32-nm CNTFET model file and Synopsis HSPICE simulator have been used to carry out the simulations at a supply of 0.9 V. The proposed circuit shows a 34.16 %, 66.44 %, and 82.80 % reduction in power, PDP, and EDP as compared to the lowest power, delay, and PDP of the designs under consideration. The performance of the multiplier is evaluated under different temperatures, supply voltages, loads, and oxide thickness.

Femtosecond laser treatment of SWNT onto metal electrodes and its effect on carbon nanotube field effect transistor

With unique electrical, mechanical, and thermal properties, carbon nanotubes (CNTs) have possessed the potential to be the ideal next-generation semiconductor in very large scale integration (VLSI). However, the extremely large schottky contact resistance generated by the interface between CNTs and metal electrodes has recently become a stricky constraint, which can greatly affect the transmission of current. In this paper, we used femtosecond laser to join the CNTs and the metal electrodes. The interconnect quality was investigated under different settings of laser power and scanning speed. Then, the carbon nanotubes field effect transistor (CNFET) based on a single CNT was fabricated and its electrical performance after laser induced interconnect was characterized. It is shown that the operating current of CNFET after irradiation is approximately 1.5 times that of before irradiation.

Advances in separation of monochiral semiconducting carbon nanotubes and the application in electronics

For over half a century, traditional silicon-based integrated circuits (ICs) have been the basis of computational electronics and are widely used in computers, cell phones, and other fields. With the rapid development of human society, silicon-based semiconductor technology is approaching its physical and engineering limits. Our increasing diversity of non-traditional computing needs, such as ultra-small, ultra-fast, ultra-low-power wearables, and space radiation protection, is driving the search for new electronic materials. Semiconducting single-walled carbon nanotubes (s-SWCNTs) have many excellent electrical properties, such as high carrier mobility and high ballistic transport, making them strong candidates for new semiconductor materials in the post-Moore era. Carbon-based electronic technology has been developed for over 20 years, and the fundamental issues such as the material purification of s-SWCNTs, preparation prospects of s-SWCNT-based field-effect transistors (CNT FETs), and device physics based on CNT FETs have been basically solved. However, the chiral diversity of s-SWCNTs may lead to problems such as fluctuations in the electrical performance of CNT FETs, limiting the application of s-SWCNTs in high-end ICs. Monochiral s-SWCNTs not only have excellent electrical properties but also have a controllable structure and uniformity, which are crucial for the high-end IC of CNTs. However, some problems exist in the purity and yield of monochiral s-SWCNT preparation and the optimization of monochiral CNT FETs. Therefore, the chiral sorting of CNTs is reviewed in this paper, and the progress of polymer reprocessing in chiral separation is highlighted. Then, the research progress of monochiral CNT FETs is introduced, and possible development directions are summarized and analyzed. Finally, the application prospects of chiral-enriched s-SWCNTs include challenges and future opportunities.

Ternary encoder and decoder designs in RRAM and CNTFET technologies

A possible way for the very large scale integration (VLSI) industry to keep up with the pace of high density, computational capability, and energy efficiency is to look into some technologies ahead of binary logic. In recent years, multiple-valued logic (MVL) has caught the notable attention of digital system designers. The carbon nanotube field effect transistor (CNTFET) has been exclusively used for the implementation of MVL circuits. Resistive random-access memory (RRAM) offers a very durable option for executing the MVL due to its capability of storing various resistance states in one cell. In this paper, a ternary 9:2 encoder and a ternary 2:9 decoder have been designed and simulated using the proposed RRAM-based ternary logic gates with standard 32nm CNTFETs. In comparison to other ternary circuits in the literature, the proposed CNTFET RRAM-based ternary logic circuits show less power consumption, delay, and power delay product (PDP). The power of the CNTFET RRAM-based proposed ternary inverter (TI), ternary NAND (TNAND), and ternary NOR (TNOR) is 32.78%, 51.48%, and 24.14% less than the lowest power of the other designs under consideration. The PVT variations and reliability of the proposed encoder and decoder circuits have also been studied.

The design of adder, subtractor, and derivative circuits without the use of op-amp in CNFET Technology

The complexity of digital circuits is constantly rising. Analog computing can be an excellent alternative to overcome the complexity issue. Operational Amplifiers play a serious role in many analog circuit designs. This paper presents a new implementation approach to an analog subtractor. This design enjoys high speed and low power dissipation using Carbon Nanotube FETs (CNTFETs). We have also achieved a significant improvement in terms of the number of transistors and chip area. The proposed design considerably decreases power consumption and optimizes the chip area. The same performance can be achieved when designing a high-quality Differentiator. It is to remark that there is no need to use a huge number of resistors and capacitors. In this design, no additional voltage or current sources have been used. HSPICE and the Stanford 32 nm CNTFET model are used to simulate the proposed circuit. The comparisons with State-of-the-art prove the performance of this design.

Solution-Processed Carbon Nanotube Field-Effect Transistors Treated by Material Post-Treatment Approaches

Solution-Processed Carbon Nanotube Field-Effect Transistors Treated by Material Post-Treatment Approaches

Plug-and-play smart transistor bio-chips implementing point-of-care diagnosis of AMI with modified CRISPR/Cas12a system

The point-of-care diagnosis of acute myocardial infarction (AMI), an extremely lethal disease with only a few hours of golden rescue time, is significant and urgently required. Here, we describe a plug-and-play carbon nanotube field effect transistor (CNT-FET) bio-chip supported with a smart portable readout for ultrasensitive and on-site testing of cardiac troponin I (cTnI), which is one of the most specific and valuable biomarkers of AMI. A modified clustered regularly interspaced short palindromic repeats (CRISPR)/Cas12a system, featuring the G-triplex structured reporter, was first combined with the CNT-FET to realize non-nucleic acid detection. Such a unique CNT-FET biosensor achieved the high sensitivity (LOD: 0.33 fg/mL), which is expected to give timely warning in the early stage of myocardial injury. In addition, a bilayer gate dielectric consisting of Y2O3/HfO2, employed into the passivation process, enabled the high environmental stability and repeatability of CNT-FET. More importantly, the homemade compact chip readout forged a field-deployable cTnI analytical tool, realizing “plasma-to-answer” performance for AMI patients in point-of-care testing scenarios. The developed technology holds promise to help doctors make clinical decisions faster, especially in remote areas.

Self‐Aligned Contact Doping for Performance Enhancement of Low‐Leakage Carbon Nanotube Field Effect Transistors

AbstractCarbon nanotube (CNT) field effect transistors (CNFETs) show promise for the next generation VLSI systems due to their excellent scalability, energy efficiency, and speed. However, high leakage current is a drawback of large diameter CNTs (diameter (DCNT) ≥ 1.4 nm) due to the small electronic band gap (EG) ≤ 0.6 eV and effective mass. This work investigates the on‐current and off‐current tradeoff for two populations of semiconducting‐enriched CNT with DCNT ≈ 1.0 nm displaying a simultaneous 50x improvement in minimun current (IMIN) with 2.5x degradation in contact resistance compared to DCNT ≈ 1.4 nm using a Pd side‐bonded contact. A method to enhance the performance of low‐leakage CNFETs is demonstrated using sub‐monolayer self‐aligned contact doping with 0.8 nm of MoOX, which delivers a 57% reduction in contact resistance to DCNT ≈ 1.0 nm. Robustness is verified after annealing at 200 °C for 30 min and monitoring stability across 6 months post‐fabrication with no change in electrical behaviors.

Aramid Nanodielectrics for Ultraconformal Transparent Electronic Skins.

On-skin electronics require minimal thicknesses and decent transparency for conformal contact, imperceptible wearing, and visual aesthetics. It is challenging to search for advanced ultrathin dielectrics capable of supporting the active components while maintaining bending softness, easy handling, and wafer-scale processability. Here, self-delaminated aramid nanodielectrics (ANDs) are demonstrated, enabling any skin-like electronics easily exfoliated from the processing substrates after complicated nanofabrication. In addition, ANDs are mechanically strong, chemically and thermally stable, transparent and breathable, therefore are ideal substrates for soft electronics. As demonstrated, compliant epidermal electrodes comprising silver nanowires and ANDs can successfully record high-quality electromyogram signals with low motion artifacts and satisfying sweat and water resistance. Furthermore, ANDs can serve as both substrates and dielectrics in single-walled carbon nanotube field-effect transistors (FETs) with a merely 160-nm thickness, which can be operated within 4V with on/off ratios of 1.4 ± 0.5 × 105 , mobilities of 39.9 ± 2.2 cm2 V-1 s-1 , and negligible hysteresis. The ultraconformal FETs can function properly when wrapped around human hair without any degradation in performance.

Impact of Parametric Variation on the Characteristics and Performance of CNTFET Inverter

In this paper, a simple carbon nanotube field effect transistor (CNTFET)-based inverter has been simulated and the impacts of changing various design and process parameters on its characteristics and performance have been analysed using HSPICE. The 32 nm CNTFET model of Stanford University has been used here for the simulation of the inverter. The simulation results and the voltage transfer characteristics (VTC) curve of the inverter have been extracted for (i) different channel lengths, (ii) top gate di-electric material thickness (tox), (iii) pitch value (iv) the number of tubes in CNTFET channel region and (v) chirality of the CNT. It has been observed that the VTC curve changes significantly with different values of these parameters. Some important output parameters like maximum dc current, power, rise time, fall time, average propagation delay, etc. have been measured in each case. Changes in maximum power consumption value due to the change in different parameter values are observed through plotted graphs. Output dc current vs. input voltage graphs have been plotted for different chirality of the tubes, the number of the tubes, and pitch values between n-type CNTFET and p-type CNTFET of the inverter.

Monolithic three-dimensional integration of RRAM-based hybrid memory architecture for one-shot learning

In this work, we report the monolithic three-dimensional integration (M3D) of hybrid memory architecture based on resistive random-access memory (RRAM), named M3D-LIME. The chip featured three key functional layers: the first was Si complementary metal-oxide-semiconductor (CMOS) for control logic; the second was computing-in-memory (CIM) layer with HfAlOx-based analog RRAM array to implement neural networks for feature extractions; the third was on-chip buffer and ternary content-addressable memory (TCAM) array for template storing and matching, based on Ta2O5-based binary RRAM and carbon nanotube field-effect transistor (CNTFET). Extensive structural analysis along with array-level electrical measurements and functional demonstrations on the CIM and TCAM arrays was performed. The M3D-LIME chip was further used to implement one-shot learning, where ~96% accuracy was achieved on the Omniglot dataset while exhibiting 18.3× higher energy efficiency than graphics processing unit (GPU). This work demonstrates the tremendous potential of M3D-LIME with RRAM-based hybrid memory architecture for future data-centric applications.

Extraction of the Contact Resistance of Carbon Nanotube Field Effect Transistors Using the Bias Extrapolation Method and Statistical Measurements

Extraction of the Contact Resistance of Carbon Nanotube Field Effect Transistors Using the Bias Extrapolation Method and Statistical Measurements

Hybrid fabrication of flexible fully printed carbon nanotube field-effect transistors

Hybrid fabrication of flexible fully printed carbon nanotube field-effect transistors

Designing high-speed and energy-efficient dynamic comparators using complementary carbon nanotube field-effect transistors

Designing high-speed and energy-efficient dynamic comparators using complementary carbon nanotube field-effect transistors

Ternary arithmetic and logic unit with carbon nanotube-based field-effect transistors for ultra-low power and high-speed applications

<span>The number of consumers for different applications has expanded tremendously as a result of the growth of consumer electronics-related applications in numerous sectors. Customers often need high-speed applications that use a minimal amount of power for a variety of applications like signal processing, picture processing, communication systems, and so on. The speed of a ternary logic-based design might be greater than that of a binary logic-based one. In this study, a novel architecture for arithmetic and logic units (ALUs) is proposed. The design makes use of ternary logic. In order to accomplish both low power consumption and high performance, methodologies for designing carbon nanotube-based field-effect transistors (CNTFETs) are employed. The method that has been suggested is able to carry out operations such as addition, subtraction, multiplication, reasoning, and comparison. After developing the recommended model, it is compared to earlier designs for power delay product (PDP), average power consumption, and maximum delay duration. The simulation findings show that the carbon nanotube field effect transistors (CNTFET) based ternary ALU circuits outperformed conventional ternary full adder circuits. The suggested design had a delay time of 13.94 ps and a PDP of 5.32 aJ, while the old design had a delay time of 17.67 ps and a PDP of 51.38 aJ.</span>

High-efficient reversible full adder realized by dynamic threshold-based gate diffusion input logics

A new 12-transistor reversible full adder (FA) is designed based on carbon-nanotube-field effect transistors (CNTFETs) with 32 nm channel length and an area of 0.2204 μm2, 1 constant input (CI), and 3 garbage outputs (GO). The FA has 3 reversible logic gates in two of its stages that are realized by the gate diffusion input (GDI) technique. In the FA, 2 Toffoli gates with 1 CI and 1 new GDI-reversible-multiplexer are used to generate Sum and Cout, respectively. The multiplexer is 3*3, with two GOs, and a significant area reduction by only two transistors. The inputs of the circuit prevent the excessive increase of GOs and CIs. The Monte Carlo analysis using the HSPICE simulator indicates a better sensitivity of the FA versus fabrication with 6.45%, 1.86%, and 8.01% improvements of maximum values of power, delay, and power-delay-product (PDP). The FA is implemented in a 4-bit, 8-bit, 16-bit, and 32-bit ripple carry adder (RCA), and its superior results are seen. Under 32-bit RCA, the proposed circuit with 4956.30 fJ shows more energy savings compared to most competitors. The extracted results, the different figure of merits (FoMs), and reversibility features represent the proposed circuit as a desirable procedure for future works.

CNTFET and RRAM Based Low Power Design of Unbalanced Ternary Logic Gates and Arithmetic Circuits

The advent of multi-valued logic (MVL) systems provides considerable improvements in energy consumption and computational efficiency compared to binary logic systems. Using resistive random-access memory (RRAM) and carbon nanotube field effect transistors (CNTFETs), this manuscript presents a new design method for ternary logic gates (standard ternary inverter (STI), ternary NOR, and ternary NAND) and some arithmetic circuit applications are implemented based on the proposed ternary logic gates. The simulations of the proposed circuits are carried out in Synopsis HSPICE software by employing 32-nm Stanford CNTFET technology along with the Stanford RRAM model. The robustness of the designed CNTFET-RRAM STI circuit is investigated for variations in process parameters. Simulation results verify that the proposed designs outperform other CNTFET based ternary logic circuits in terms of number of components, power consumption, delay and power delay product (PDP). Furthermore, a reduced change is perceived with respect to power consumption and PDP of the presented logic gates with process deviation, and variations in supply voltage, temperature, capacitance and frequency. The presented STI, TNAND, TNOR, ternary half adder (THA) and ternary multiplier (TMUL) circuits exhibit an improvement in PDP with less transistor count as compared to the other existing designs in the literature.

Novel Second-Order Fully Differential All-Pass Filter Using CNTFETs.

In this paper, a new carbon nanotube field effect transistor (CNTFET)-based second-order fully differential all-pass filter circuit is presented. The realized filter uses CNTFET-based transconductors and grounded capacitors. An active-only second-order fully differential all-pass filter circuit topology is also presented by replacing the grounded capacitance with a CNTFET-based varactor to achieve filter tunability. By controlling the varactor capacitance, active-only second-order fully differential all-pass filter tunability in the range of 15 GHz to 27.5 GHz is achieved. The proposed active-only circuit works on -oltage, low-power dissipation and high tunable pole frequency. The realized circuit operations are verified through the HPSPICE simulation tool. Deng's CNTFET model is utilized to verify the filter performances at the 16 nm technology node. It is seen that the proposed filter simulation justifies the theoretical predictions and works efficiently in the deep-submicron technology.

Performance Enhancement of CNFET-based Approximate Compressor for Error Resilient Image Processing

The approximate computing has emerged as an appealing approach to minimize energy consumption. By implementing inexact circuits at the transistor level, significant enhancements in various performance metrics such as power consumption, delay, energy, and area can be achieved. Consequently, researchers worldwide have been actively exploring the application of inexact techniques in circuit design. This paper introduces a novel technique for designing low-power digital circuits called extremely low power modified gate diffusion input (ELP-MGDI). This technique combines the principles of Modified Gate Diffusion Input with the utilization of Carbon Nano Tube Field-Effect Transistors (CNTFETs). The Objective of this paper is to enhance the power, delay, and area characteristics of a 4:2 compressor and multiplier by employing ELP-MGDI approach. To achieve this, we conducted thorough analysis and simulations using the Verilog-A simulator 32 nm CNFET technology Stanford University within the Cadence Virtuoso Tool. The results show extremely power, delay reduction and power-delay-product (PDP) of approximate multiplier has been improved by over 99%, and the circuit area has been reduced by 55%. The proposed processing module demonstrates superior performance compared to their conventional counterparts.