Capacitorless Memory Research Articles

Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless Memory

Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless Memory

Fully bulk CMOS compatible Key Shape Floating Body Memory (KFBM)

This paper presents a capacitorless memory cell with bulk CMOS compatibility, consisting of a MOSFET with a virtual floating body formed by the trench. The name Key shape Floating Body Memory (KFBM) is derived from the resemblance of the structure to the shape of an antique key. The carrier concentration in the vertical device beneath the MOSFET results in over more than 5 orders of magnitude of the on–off cell current ratio with off-current less than 100pA/cell. The device achieves a retention time of about 1 s at 85C and over 10 s at 27C all the while maintaining high density and scalability. On the basis of TCAD simulation we have demonstrated high tolerance to disturbance (more than 1000 times with all types of signals), which has been an issue with DRAM memories. KFBM can incorporate both dynamic RAM and flash features.

Micro-features of ambipolar snapback behaviour under high current injection to design capacitorless memory device

This paper presents micro-features of capacitorless memory cells based on snapback phenomenon and modeling of space-charges. 2—Dimensional gate grounded NMOS structure is specified and its operational window of the memory cell is inspected using the Synopsys TCAD tool. This work examines snapback behaviour in one transistor DRAM memory cell in the absence of a storage capacitor under zero gate bias and applied ramp of high current at the drain terminal. Carrier electrostatics and memory cell mechanisms are also explored by adjusting the slope of the high current ramp. The process variation is examined for different parameters in the device. The current crowding phenomenon due to the injection of electrons and holes is investigated, giving rise to ambipolar behaviour. Due to the snapback, redistribution of electron and hole current is investigated. This work also evaluates the impact on electrostatic potential along channel and bulk under the snapback. It explains the dependency of snapback on potential build-up. Post-snapback electron current flipping presents the flow line near the gate region. The bipolar activity is manifested in surface and bulk regions to show its impact through analytics. The effect of gate biasing is also examined under the applied current ramp.

Impact ionization-induced bistability in CMOS transistors at cryogenic temperatures for capacitorless memory applications.

Cryogenic operation of complementary metal oxide semiconductor (CMOS) silicon transistors is crucial for quantum information science, but it brings deviations from standard transistor operation. Here, we report on sharp current jumps and stable hysteretic loops in the drain current as a function of gate voltage V G for both n- and p-type commercial-foundry 180-nm-process CMOS transistors when operated at voltages exceeding 1.3 V at cryogenic temperatures. The physical mechanism responsible for the device bistability is impact ionization charging of the transistor body, which leads to effective back-gating of the inversion channel. This mechanism is verified by independent measurements of the body potential. The hysteretic loops, which have a >107 ratio of high to low drain current states at the same V G, can be used for a compact capacitorless single-transistor memory at cryogenic temperatures with long retention times.

Charge-Plasma-Based Doping-Less Vertical Thyristor for Highly Integrated Volatile Memory-Cell

Conventional dynamic random-access memory (DRAM) has been facing a severe challenge to scale down to 10 nm size. Since the cell capacitor should be able to store sufficient charges of 25~30 fF/cell, high aspect ratio of cell capacitor is inevitable, resulting in capacitors leaning into each other. To overcome this issue coming from capacitor, the two-terminal vertical thyristor-based capacitorless memory was proposed as a candidate to replace current DRAM, which consists of n++-emitter/p+-base/n+-base/p++-emitter vertical structure using conventional Si technology. The two-terminal vertical thyristor-based capacitorless memory cell having n++-emitter/p+-base/n+-base/p++-emitter structure utilizes latch-up and -down features showing bi-stable current-voltage (I-V) characteristics, so that data 0 (D0) and data 1 (D1) states can be distinguished. Nevertheless, in two-terminal vertical thyristor-based capacitorless memory, in-situ doped epitaxial growth process of silicon layers is essential. As is well known, the major disadvantage of epitaxial growth process is low throughput ratio. Besides, it is difficult to form step junctions since the dopants diffuse out from their original position during the serial epi-processes due to the high process temperature. Diffusion of dopants near the junctions is unavoidable in conventional doped thyristor memory cell fabricated with epitaxial growth, as shown in SIMS profile of Fig. 1(a). By applying the concept of charge plasma, the novel doping-less vertical thyristor as volatile memory is proposed, as shown in Fig. 1(b). In contrast with conventional doped thyristor memory cells, doping-less thyristor memory cells have step junction, as shown in carrier concentration profile of Fig. 1(c). Consequently, the vertical energy band diagram for doping-less thyristor memory cells differ from that of doped thyristor memory cells, as shown in Fig. 1(d). In addition, the conventional thyristor memory cells have been suffered from off-state leakage current because of the misfit dislocations at the highly doped junctions. On the other hand, the doping-less thyristor memory cells are misfit dislocation-free as their junctions are formed by the charge plasma, not the dopants. Moreover, the coulomb scattering can be dramatically reduced in doping-less thyristor memory cells owing to the absence of dopant and space charge, leading to the higher carrier mobility. As a result, the doping-less thyristor memory cells have lower off-state leakage current and higher on-state current, as shown in the I-V curves of Fig. 1(e) and (f). In this work, the effect of gap oxide thickness, which decides the intrinsic layer thickness, on latch-up voltage was investigated as well. In addition, the impact of p- and n-base metal work-function on the latch-up voltage of doping-less thyristor memory cell was investigated. Finally, the optimized metal work-function and gap oxide thickness for the memory cell were discussed. Acknowledgment* This research was supported by Brain Korea 21 PLUS Program in 2020, the MOTIE (Ministry of Trade, Industry & Energy 10069063) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Figure 1

A2RAM compact modeling: From DC to 1T-DRAM memory operation

In this work, we present a compact modeling of capacitorless A2RAM memory cell. It is obtained by combining A2RAM DC compact model with an equivalent circuit that mimics the memory state. The DC modeling is achieved by considering the A2RAM architecture as the combination of a SOI transistor in parallel with a variable-resistance bridge. The crucial aspect is the analytical description of the bridge threshold voltage. The complete A2RAM compact model is implemented in Verilog-A to allow the use of SPICE simulator. DC and memory characteristics are validated by TCAD. SPICE simulations show the operation of 2 × 2 A2RAM matrix.

Sharp Logic Switch Based on Band Modulation

The capability of Z2-FET (Zero Impact Ionization and Zero Subthreshold Slope FET) to operate as a sharp logic switch is demonstrated in advanced FD-SOI (Fully Depleted SOI) technology. The operation mechanism is band-modulation which enables remarkable DC performance in terms of ON/OFF current ratio and sharp switch (~1 mV/decade). Z2-FETs have successfully been used for ESD protection and capacitorless DRAM memory, but the presence of an inherent hysteresis has handicapped so far logic applications. However, this letter shows that fast pulses on the gate result in hysteresis-free switching: the device turns ON and OFF at same gate bias. The sharpness of the switch depends on device parameters, bias and speed of operation. Systematic experiments compare the performance of Z2-FETs with dual or single ground-planes.

A Semi-Floating Gate Memory Based on SOI Substrate by TCAD Simulation

Over the past decade, the dimensional scaling of semiconductor electronic devices has been facing fundamental and physical challenges, and there is currently an urgent need to increase the ability of dynamic random-access memory (DRAM). A semi-floating gate (SFG) transistor has been proposed as a capacitor-less memory with faster speed and higher density as compared with the conventional one-transistor one-capacitor (1T1C) DRAM technology. The integration of SFG-based memory on the silicon-on-insulator (SOI) substrate has been demonstrated in this work by using the Sentaurus Technology Computer-Aided Design (TCAD) simulation. An enhancement in retention characteristics, anti-disturbance ability, and fast writing capability, have been illustrated. The device exhibits a low operation voltage, a large threshold voltage window of ~3 V, and an ultra-fast writing of 4 ns. In addition, the SOI-based memory has shown a much-improved anti-irradiation capability compared to the devices based on bulk silicon, which makes it much more attractive in broader applications.

Effect of Schottky Contact Emitter on Electrical Characteristics in 2-Terminal Vertical Thyristor Based Capacitorless Memory

Conventional dynamic random access memory (DRAM) has been facing a severe challenge to scale down to 10 nm size. Since the cell capacitor should be able to store sufficient charges of 25~30 fF/cell, high aspect ratio of cell capacitor is inevitable, resulting in capacitors leaning into each other. To overcome this issue coming from capacitor, the vertical thyristor-based two-terminal capacitorless memory was proposed as a promising candidate to replace current DRAM, which consists of n++-emitter/p+-base/n+-base/p++-emitter vertical structure using conventional Si technology. The two-terminal vertical thyristor based capacitorless memory cell having n++-emitter/p+-base/n+-base/p++-emitter structure could be implemented as cross-point memory array cells, as shown in Fig. 1. It utilizes latch-up features showing bi-stable current-voltage (I-V) characteristics, so that data 0 (D0) and data 1 (D1) states can be distinguished. Nevertheless, in two-terminal vertical thyristor based capacitorless memory, the latch-up and latch-down voltages decrease as the operation temperature increases, resulting in narrow memory window, as shown in Fig. 2. This is attributed to the fact that the carrier diffusion barrier decreases and carrier concentrations accumulated in base region required to generate latch-up decrease with increasing operation temperature. In our study, therefore, we propose two-terminal vertical thyristor based capacitorless memory with metal emitter replacing n++-emitter in order to reduce the temperature dependency of latch-up and latch-down voltages. The thermal conductivity of metal emitter is generally higher than that of silicon n++-emitter resulting in easier radiation of heat within the device. In addition, metal-emitter/p+-base/n+-base/p++-emitter structure can reduce the temperature dependency of latch-up and latch-down voltages since the metal emitter is immune to the decrease of bandgap with increasing temperature, unlike the silicon n++-emitter. We demonstrated the I-V characteristics depending on operation temperature of two-terminal vertical thyristor based capacitorless memory cell. Furthermore, we calculated the change of the bandgap of silicon and the magnitude of schottky barrier between metal emitter and p+-base junction in order to verify the effect of metal emitter on temperature dependency of latch-up and latch-down voltages. In addition, the heat flow and the dependency of the I-V characteristics on the metal emitter were investigated by TCAD simulation. Finally, we present the effect of schottky contact emitter on electrical characteristics in two-terminal vertical thyristor based capacitorless memory. Acknowledgment * This research was supported by Brain Korea 21 PLUS Program in 2019, the MOTIE (Ministry of Trade, Industry & Energy 10069063) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Figure 1

A Semi-Floating Gate Memory with Tensile Stress for Enhanced Performance

With the continuous scaling down of devices, traditional one-transistor one-capacitor dynamic random access memory (1T-1C DRAM) has encountered great challenges originated from the large-volume capacitor and high leakage current. A semi-floating gate transistor has been proposed as a capacitor-less memory with ultrafast speed and silicon-compatible technology. In this work, a U-shaped semi-floating gate memory with strain technology has been demonstrated through TCAD simulation. Ultra-high operation speed on a timescale of 5 ns at low operation voltages (≤ 2.0 V) has been obtained. And the tensile stress induced in its channel region by using contact etch stop layer (Si3N4 capper layer) was found to significantly improve the drain current by 12.07%. Furthermore, this device demonstrated a favorable retention performance with a retention time over 1 s, and its immunity to disturbance from bit-line has also been investigated that could maintain data under the continuous worst writing disturbance operation over 10 ms.

Investigation of thin gate-stack Z2-FET devices as capacitor-less memory cells

Thin-oxide Z2-FET cells operating as capacitor-less DRAM devices are experimentally demonstrated. Both the retention time and memory window demonstrate the feasibility of implementing this cell in advanced 28 nm node FDSOI technology. Nevertheless a performance drop and higher variability with respect to thicker oxide Z2-FET cells are observed.

Doping profile extraction in thin SOI films: Application to A2RAM

We propose for the first time a method based on C-V measurement to extract the bridge doping profile which governs the operation and performance of A2RAM capacitorless memory cell. Assessed with TCAD simulation and simple extraction model adapted from bulk devices, this technique is validated with experimental data.

Effect of Misfit Dislocations in Junctions and Base Thickness on Latch-up Characteristics in Two-Terminal Vertical Thyristor-Based Capacitorless Memory

Conventional dynamic random access memory (DRAM) has been facing a severe challenge to scale down to 10 nm size. The cell capacitor should be able to store sufficient charges of 25~30 fF/cell. In order to meet this requirement, high aspect ratio of cell capacitor is inevitable, resulting in capacitors leaning into each other. To overcome this issue coming from capacitor, the vertical thyristor-based two-terminal capacitorless memory was proposed as a promising candidate to replace current DRAM, which consists of p++-anode / n+-base / p+-base / n++-cathode vertical structure using conventional Si technology. The two-terminal vertical thyristor-based capacitorless memory cell having p++-anode / n+-base / p+-base / n++-cathode vertical structure is easy to construct cross-point memory array cells, as shown in Figure 1. Furthermore, Two-terminal vertical thyristor-based capacitorless memory array cells can be operated without selector since sneak current is suppressed by latch-down process. In our study, three types of two-terminal vertical thyristor-based capacitorless memory cells consist of top-p++-anode / n+-base / p+-base / bottom-n++-cathode with 80-nm-thick base region (PNPN80), top-p++-anode / n+-base / p+-base / bottom-n++-cathode with 160-nm-thick base region (PNPN160), and top-n++-cathode / p+-base / n+-base / bottom-p++-anode with 160-nm-thick base region (NPNP160) were fabricated, individually. The dopant concentration profile of each device was analyzed by secondary ion mass spectroscopy (SIMS), as shown in Figure 2. By correlating HR TEM images with SIMS analyses, misfit dislocations were observed at the depth where dopant pile-up was found, as shown in Figure 3. Figure 4 (a), (b) and (c) show I-V measurements of PNPN80, PNPN160 and NPNP160, respectively. The difference of latch-up voltages between Figure 4 (b) and (c) can be explained by carrier life-time difference. NPNP160 had less misfit dislocations compared to PNPN160, resulting in longer excess carrier life-time, since dislocations act as recombination centers. Thus, NPNP160 needed smaller anode voltage to induce sufficient excess carriers in base regions, which had smaller latch-up voltage than PNPN160. In addition, the difference of latch-up voltages between Figure 4 (a) and (b) resulting from base thickness difference can be explained by electric field. The electric field of PNPN160 is weaker than that of PNPN80 in base regions when equivalent anode voltage is applied. Therefore, PNPN160 needed larger anode voltage to lower the injection barrier of excess carriers. Besides, the effect of misfit dislocations and base dopant concentration on memory margin and off-state leakage current will be discussed. Finally, the memory cell pulse operations will be exhibited as well. Acknowledgment * This research was supported by Brain Korea 21 PLUS Program in 2018, the MOTIE (Ministry of Trade, Industry & Energy 10069063) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Figure 1

1-T Capacitorless DRAM Using Laterally Bandgap Engineered Si-Si:C Heterostructure Bipolar I-MOS for Improved Sensing Margin and Retention Time

In this paper, a single transistor (1-T) capacitorless DRAM using laterally bandgap engineered Si-Si:C heterostructure bipolar I-MOS is investigated using 2-D calibrated simulations. The proposed device features a high-K gate dielectric, a metal gate, and an epitaxially grown Si0.99C0.01 source/drain regions. Due to lattice mismatch between the Si:C source/drain and the Si channel and resultant strain effect, the proposed 1-T capacitorless DRAM memory cell exhibits enhanced memory characteristics, particularly the sensing margin and the retention time. The proposed 1-T capacitorless DRAM exhibits a sensing margin of the order of ∼1.5 μA/μm and ∼2.0 μA/μm for the temperatures T = 300 K and T = 358 K, respectively. Also, the proposed 1-T capacitorless DRAM memory cell shows a retention time of ∼1.68 s and ∼845 ms for T = 300 K and T = 358 K, respectively. Therefore, the proposed 1-T capacitorless memory has a greater potential to replace existing 1-T capacitorless DRAM memory.

A review of the Z2-FET 1T-DRAM memory: Operation mechanisms and key parameters

The band-modulation and sharp-switching mechanisms in Z2-FET device operated as a capacitorless 1T-DRAM memory are reviewed. The main parameters that govern the memory performance are discussed based on detailed experiments and simulations. This 1T-DRAM memory does not suffer from super-coupling effect and can be integrated in sub-10 nm thick SOI films. It offers low leakage current, high current margin, long retention, low operating voltage especially for programming, and high speed. The Z2-FET is suitable for embedded memory applications.

Investigation of tunnel field-effect transistors as a capacitor-less memory cell

In this work, we report experimental results on the use of tunnel field-effect transistors as capacitorless dynamic random access memory cells, implemented as double-gate fully depleted silicon-on-insulator devices. The devices have an asymmetric design, with a partial overlap of the top gate (LG) and with a total overlap of the back gate over the channel region (LG + LIN). A potential well is created by biasing the back gate (VBG) in accumulation, while the front gate (VFG) is in inversion. Holes from the p+ source are injected by the forward-biased p+ i junction and stored in the electrically induced potential well.

A vertically integrated capacitorless memory cell

A two-port capacitorless PNPN device with high density, high speed and low power memory fabricated using standard CMOS technology is presented. Experiments and calibrated simulations were conducted which prove that this new memory cell has a high operation speed (ns level), large read current margin (read current ratio of 104×), low process variation, good thermal reliability and available retention time (190 ms). Furthermore, the new memory cell is free of the cyclic endurance/reliability problems induced by hot-carrier injection due to the gateless structure.

Capacitor-less memory cell fabricated on nano-scale strained Si on a relaxed SiGe layer-on-insulator

We investigated the combined effect of the strained Si channel and hole confinement on the memory margin enhancement for a capacitor-less memory cell fabricated on nano-scale strained Si on a relaxed SiGe layer-on-insulator (ε-Si SGOI). The memory margin for the ε-Si SGOI capacitor-less memory cell was higher than that of the memory cell fabricated on an unstrained Si-on-insulator (SOI) and increased with increasing Ge concentration of the relaxed SiGe layer; i.e. the memory margin for the ε-Si SGOI capacitor-less memory cell (138.6 µA) at a 32 at% Ge concentration was 3.3 times higher than the SOI capacitor-less memory cell (43 µA).

Experimental Demonstration of Capacitorless A2RAM Cells on Silicon-on-Insulator

We report the fabrication and characterization of A2RAM capacitorless memory cell on silicon-on-insulator (SOI). Holes and electrons are separated in two superposed p- and n-channel regions. The retrograde p-n doping in a 36-nm-thick body has been successfully tailored by epitaxial regrowth, without any alteration of the CMOS/SOI process. We document the detailed device operation and its attractive performance in terms of current margin, retention time, and variability.

A multi-level capacitor-less memory cell fabricated on a nano-scale strainedsilicon-on-insulator

A multi-level capacitor-less memory cell was fabricated with a fully depletedn-metal–oxide–semiconductor field-effect transistor on a nano-scale strained silicon channelon insulator (FD sSOI n-MOSFET). The 0.73% biaxial tensile strain in the siliconchannel of the FD sSOI n-MOSFET enhanced the effective electron mobility to ∼ 1.7 times that with an unstrained silicon channel. This thereby enables both front- and back-gate celloperations, demonstrating eight-level volatile memory-cell operation with a 1 ms retention time and12 µA memory margin. This is a step toward achieving a terabit volatile memory cell.