Abstract

With the continuous scaling down of devices, traditional one-transistor one-capacitor dynamic random access memory (1T-1C DRAM) has encountered great challenges originated from the large-volume capacitor and high leakage current. A semi-floating gate transistor has been proposed as a capacitor-less memory with ultrafast speed and silicon-compatible technology. In this work, a U-shaped semi-floating gate memory with strain technology has been demonstrated through TCAD simulation. Ultra-high operation speed on a timescale of 5 ns at low operation voltages (≤ 2.0 V) has been obtained. And the tensile stress induced in its channel region by using contact etch stop layer (Si3N4 capper layer) was found to significantly improve the drain current by 12.07%. Furthermore, this device demonstrated a favorable retention performance with a retention time over 1 s, and its immunity to disturbance from bit-line has also been investigated that could maintain data under the continuous worst writing disturbance operation over 10 ms.

Highlights

  • The large volume capacitor of the one transistor (1T)-one capacitor (1C) DRAM has limited its further applications in advanced memory fields with shrinking cell size [1,2,3]

  • The drain current of the semi-floating gate transistor (SFGT) is relatively small leading to unsatisfactory sensing capabilities due to the tunneling mechanism which is similar to that of traditional tunneling field-effect transistor (TFET) devices

  • The read-out current almost keeps unchanged. When it is disturbed by the VD -write-1 operation, the embedded TFET is weakly turned on such that charges are written into the semi-floating gate gate (SFG) slowly

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Summary

Introduction

The large volume capacitor of the one transistor (1T)-one capacitor (1C) DRAM has limited its further applications in advanced memory fields with shrinking cell size [1,2,3]. The employment of strain technologies in modern electronic devices to improve mobility and drive current has been developed for decades in advanced complementary metal-oxide-semiconductor (CMOS) transistors [10,11,12,13,14,15]. Most of these technologies, such as embedded SiGe [10] and embedded Si:C [13], request complex process steps, making them not suitable or transferrable to a wider range of advanced processes.

Device Structure and Operation
Effect of the Tensile-Stress CESL
Effect of the Tensile-Stress
It is foundofthat the memory read-out has current state
Retention and Disturbance Performance
Findings
Conclusions

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