Charge-Plasma-Based Doping-Less Vertical Thyristor for Highly Integrated Volatile Memory-Cell

Abstract

Conventional dynamic random-access memory (DRAM) has been facing a severe challenge to scale down to 10 nm size. Since the cell capacitor should be able to store sufficient charges of 25~30 fF/cell, high aspect ratio of cell capacitor is inevitable, resulting in capacitors leaning into each other. To overcome this issue coming from capacitor, the two-terminal vertical thyristor-based capacitorless memory was proposed as a candidate to replace current DRAM, which consists of n++-emitter/p+-base/n+-base/p++-emitter vertical structure using conventional Si technology. The two-terminal vertical thyristor-based capacitorless memory cell having n++-emitter/p+-base/n+-base/p++-emitter structure utilizes latch-up and -down features showing bi-stable current-voltage (I-V) characteristics, so that data 0 (D0) and data 1 (D1) states can be distinguished. Nevertheless, in two-terminal vertical thyristor-based capacitorless memory, in-situ doped epitaxial growth process of silicon layers is essential. As is well known, the major disadvantage of epitaxial growth process is low throughput ratio. Besides, it is difficult to form step junctions since the dopants diffuse out from their original position during the serial epi-processes due to the high process temperature. Diffusion of dopants near the junctions is unavoidable in conventional doped thyristor memory cell fabricated with epitaxial growth, as shown in SIMS profile of Fig. 1(a). By applying the concept of charge plasma, the novel doping-less vertical thyristor as volatile memory is proposed, as shown in Fig. 1(b). In contrast with conventional doped thyristor memory cells, doping-less thyristor memory cells have step junction, as shown in carrier concentration profile of Fig. 1(c). Consequently, the vertical energy band diagram for doping-less thyristor memory cells differ from that of doped thyristor memory cells, as shown in Fig. 1(d). In addition, the conventional thyristor memory cells have been suffered from off-state leakage current because of the misfit dislocations at the highly doped junctions. On the other hand, the doping-less thyristor memory cells are misfit dislocation-free as their junctions are formed by the charge plasma, not the dopants. Moreover, the coulomb scattering can be dramatically reduced in doping-less thyristor memory cells owing to the absence of dopant and space charge, leading to the higher carrier mobility. As a result, the doping-less thyristor memory cells have lower off-state leakage current and higher on-state current, as shown in the I-V curves of Fig. 1(e) and (f). In this work, the effect of gap oxide thickness, which decides the intrinsic layer thickness, on latch-up voltage was investigated as well. In addition, the impact of p- and n-base metal work-function on the latch-up voltage of doping-less thyristor memory cell was investigated. Finally, the optimized metal work-function and gap oxide thickness for the memory cell were discussed. Acknowledgment* This research was supported by Brain Korea 21 PLUS Program in 2020, the MOTIE (Ministry of Trade, Industry & Energy 10069063) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Figure 1