Capacitor-less memory cell fabricated on nano-scale strained Si on a relaxed SiGe layer-on-insulator

Abstract

We investigated the combined effect of the strained Si channel and hole confinement on the memory margin enhancement for a capacitor-less memory cell fabricated on nano-scale strained Si on a relaxed SiGe layer-on-insulator (ε-Si SGOI). The memory margin for the ε-Si SGOI capacitor-less memory cell was higher than that of the memory cell fabricated on an unstrained Si-on-insulator (SOI) and increased with increasing Ge concentration of the relaxed SiGe layer; i.e. the memory margin for the ε-Si SGOI capacitor-less memory cell (138.6 µA) at a 32 at% Ge concentration was 3.3 times higher than the SOI capacitor-less memory cell (43 µA).