A multi-level capacitor-less memory cell fabricated on a nano-scale strainedsilicon-on-insulator

Abstract

A multi-level capacitor-less memory cell was fabricated with a fully depletedn-metal–oxide–semiconductor field-effect transistor on a nano-scale strained silicon channelon insulator (FD sSOI n-MOSFET). The 0.73% biaxial tensile strain in the siliconchannel of the FD sSOI n-MOSFET enhanced the effective electron mobility to ∼ 1.7 times that with an unstrained silicon channel. This thereby enables both front- and back-gate celloperations, demonstrating eight-level volatile memory-cell operation with a 1 ms retention time and12 µA memory margin. This is a step toward achieving a terabit volatile memory cell.