Capacitively-coupled Instrumentation Amplifier Research Articles

A novel tunable capacitively-copuled instrumentation amplifier with 14.4 nV/ [formula omitted] z) noise and 190.47 nW micro-power for ECG applications

This paper describes a low-power, low-noise capacitively-coupled instrumentation amplifier (CCIA) designed for capturing biopotential signals. The main advantage of proposed design are as (i) CCIA based on new IA has been proposed, (ii) the lower cutoff frequency has been improved by adding MOS based resistor, (iii) gm enhancement circuit is added in operational transconductance amplifier (OTA) based fully differential difference amplifier (FDDA)to improve gain and bandwidth. The DC electrode-offset voltage is reduced and the input impedance is increased by using feedback mechanism. Cadence EDA tool is used to analyze the findings of the proposed CCIA's in 0.18 μm, CMOS technology with a 1.8 V power supply. The proposed CCIA architecture has an adjustable mid-band gain from 52.55 to 61.11 dB for bias voltage ranges from 0.1 to 0.6 V, frequency range of 0.06 Hz–1.72 kHz, and a CMRR of 122 dB. The proposed CCIA has a total power dissipation of 190.47 nW and equivalent input referred noise (IRN) of 14.4 nV/sqrtHz at 0.01 Hz. It only occupies 0.01 mm2 of core area. To assess the robustness of suggested design, PVT analysis, post layout simulation and a comparison with previously published works demonstrates the competence of the design.

Design of a Configurable 4-Channel Analog Front-End for EEG Signal Acquisition on 180nm CMOS Process

In this work, a 4-channel Analog Front-End (AFE) circuit has been proposed for EEG signal recording. For EEG recording systems, the AFE may handle a wide range of sensor inputs with high input impedance, adjustable gain, low noise, and wide bandwidth. The buffer or current-to-voltage converter block (BCV), which can be set to operate as a buffer or a current-to-voltage converter circuit, is positioned between the electrode and the main amplifier stages of the AFE to achieve high input impedance and work with sensor signal types. A chopper capacitively-coupled instrumentation amplifier (CCIA) is positioned after the BCV as the main amplifier stage of the AFE to reduce input-referred noise and balance the impedance of the overall AFE system. A programmable gain amplifier (PGA) is the third stage of the AFE that allows the overall gain of the AFE to be adjusted. The suggested AFE operates in a wide frequency range of 0.5 Hz to 2 kHz with a high input impedance bigger than 2TΩ, and it is constructed and simulated using a 180nm CMOS process. With the lowest 100-dB CMRR and low input-referred noise of 1.8 µVrms, the AFE can achieve low noise efficiency. EEG signals can be acquired with this AFE system, which is very useful for detecting epilepsy and seizures.

A CMOS Hall Sensors Array With Integrated Readout Circuit Resilient to Local Magnetic Interference From Current-Carrying Traces

This paper proposes a CMOS Hall sensors array with readout circuitry to counteract the magnetic interference from nearby conductors carrying high currents. The 3×3 Hall sensors array with current-spinning collects the spatial magnetic field information in a time-interleaved manner while the readout circuitry, formed by a capacitively-coupled instrumentation amplifier (CCIA) with T-capacitor feedback network, amplifies the transduced signals for subsequent processing. The calibration mechanism analyzes the magnetic field distribution on the array and separates the magnetic field component due to the environment and local perturbation from adjacent traces, enabling accurate detection of the environmental magnetic field. Prototyped in a 0.35-μm CMOS process, the Hall sensors array and readout circuit occupy an area of 2.2 × 2.2 mm2 and consume 3.5 mA of current under a 3.3-V supply. The hall sensors achieve an average sensitivity of 100 V/(A·T). The input-referred noise of the entire circuit is 0.128 μT/√Hz. With the interference cancellation scheme, the error in the magnetic field readings caused by a conductor 5 mm from the center of the chip carrying 3 A of current reduced from 120 to 5 μT, corresponding to a 24× improvement. Overall, the average error of the captured magnetic field after calibration reaches 0.9%.

A 17.6-Bit 800-SPS Energy-Efficient Read-Out IC With Input Impedance Boosting

A 17.6-bit, 800-sample-per-second (SPS) read-out integrated circuit has been implemented for a bridge sensor. The read-out integrated circuit has a capacitively-coupled instrumentation amplifier (CCIA) with a sensor offset voltage compensation circuit, an amplifier offset voltage compensation circuit, and an input impedance boosting loop (IBL). Followed by the CCIA, a programmable-gain third-order discrete-time incremental delta-sigma (ΔΣ) analog-to-digital converter (ADC) with an output data-rate of 12.8 kHz shortens the sensing time to reduce the static power consumption of the resistive bridge sensor and the read-out IC. To boost the input impedance of the CCIA, the system-level input and output choppers operate at a frequency of 12.8 kHz. The ΔΣ modulator converts the modulated signal to digital with a sampling clock of 4 MHz. The system-level chopping reduces the residual offset and the low-frequency noise with an on-chip cascade of integrators (CoI) filter. Implemented in a 0.13 μm CMOS process, the read-out circuit achieves an input impedance of 22 MΩ at a data-rate of 800 SPS, a sensor offset compensation range of ± 350 mV, a maximum effective resolution of 17.6 bits, and an input-referred noise of 1.72 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RMS</sub> at a gain of 128. It draws an average current of 106.3 μA from a 3 V supply and 1.3 μA from a 1.5 V supply.

3.6 mW Active-Electrode ECG/ETI Sensor System Using Wideband Low-Noise Instrumentation Amplifier and High Impedance Balanced Current Driver.

An active electrode (AE) and back-end (BE) integrated system for enhanced electrocardiogram (ECG)/electrode-tissue impedance (ETI) measurement is proposed. The AE consists of a balanced current driver and a preamplifier. To increase the output impedance, the current driver uses a matched current source and sink, which operates under negative feedback. To increase the linear input range, a new source degeneration method is proposed. The preamplifier is realized using a capacitively-coupled instrumentation amplifier (CCIA) with a ripple-reduction loop (RRL). Compared to the traditional Miller compensation, active frequency feedback compensation (AFFC) achieves bandwidth extension using the reduced size of the compensation capacitor. The BE performs three types of signal sensing: ECG, band power (BP), and impedance (IMP) data. The BP channel is used to detect the Q-, R-, and S-wave (QRS) complex in the ECG signal. The IMP channel measures the resistance and reactance of the electrode-tissue. The integrated circuits for the ECG/ETI system are realized in the 180 nm CMOS process and occupy a 1.26 mm2 area. The measured results show that the current driver supplies a relatively high current (>600 μApp) and achieves a high output impedance (1 MΩ at 500 kHz). The ETI system can detect resistance and capacitance in the ranges of 10 mΩ-3 kΩ and 100 nF-100 μF, respectively. The ECG/ETI system consumes 3.6 mW using a single 1.8 V supply.

A Low-Power Single-Path Bio-Impedance Measurement System Using an Analog-to-Digital Converter for I/Q Demodulation.

In this paper, a low power single-path bio-impedance (Bio-Z) measurement system for early detection of acute myocardial ischemia is presented. The fully integrated system consists of a current source, an amplifier, and an analog-to-digital converter (ADC). The system utilizes the in-phase and quadrature (I/Q) components to obtain the real and imaginary parts of the tissue impedance. To achieve this goal, the ADC has been used to separate the I/Q components in addition to digitizing the samples. This can lead to power and silicon area reduction. The proposed circuit exploits the benefits of capacitively-coupled instrumentation amplifier, including inherent DC cancellation, low power, low noise, and high linearity and is implemented in 0.18 µm CMOS technology with a 1 V power supply. This system is designed and tested using a pseudo-sine 2 µAP-P current with a frequency of 1 kHz. The system can measure an input impedance that varies over a range from 0.03-7.5 kΩ with a resolution of 0.766 Ωrms while consuming 2 µW power from the supply. The operation of the system is also shown in the recording of impedance variation with respiration and heartbeat.

Temperature-insensitive Pseudo-resistor

A novel pseudo-resistor insensitive to temperature change is proposed. In order for the pseudo-resistor implemented in the previous capacitively coupled instrumentation amplifier (CCIA) or transimpedance amplifier (TIA) to be used in the industrial temperature range (-40 ℃ to 85 ℃), it is necessary to develop a pseudo resistor insensitive to temperature change. The new pseudo-resistor can adjust the resistance value and the temperature sensitivity can be tuned. The pseudo-resistor is implemented using two PMOSs connected in series and a gate bias control block. A current proportional to the absolute temperature is used to control the magnitude of the pseudo-resistance and its temperature sensitivity. It was designed and laid out based on the 0.18 μm CMOS process, and as a result of simulation, it was possible to adjust the resistance value between 1.7 GΩ and 10.4 GΩ. The temperature sensitivity of the pseudo-resistor was able to obtain a minimum value of 91 ppm/℃ in the range of -40 ℃ to 85 ℃.

A CMRR enhancement circuit by employing auxiliary buffer of capacitively coupled instrumentation amplifier for neural signal recording

Here, a common-mode rejection ratio (CMRR) enhancement circuit is proposed by employing an auxiliary buffer (AB) to the pseudo resistors of the capacitively coupled instrumentation amplifier (CCIA). After applying AB to CCIA, the differential-mode gain remains the same with an extended bandwidth, and the common-mode gain is reduced, and therefore, the CMRR is enhanced.

A Capacitively Coupled CT Δ ΣM With Chopping Artifacts Rejection for Sensor Readout ICs

This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time ΔΣ modulator (CT ΔΣM) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and 1/f noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency ( f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</sub> ) same as the sampling frequency ( f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> ). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT ΔΣM. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , drawing 232.2 μA at a 1.8 V supply. The proposed capacitively coupled (CC)-CT ΔΣM has a 19.4 nV/ √{Hz} input-referred noise density, 1.9 μV offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> . With -110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique.

A CMRR Enhancement Circuit Employing Gₘ-Controllable Output Stages for Capacitively Coupled Instrumentation Amplifiers

The capacitively coupled instrumentation amplifier (CCIA) is broadly used for neural signal acquisition. Although it is suitable for various biopotential recording applications, the CCIA is vulnerable to capacitor mismatches, which degrades the common-mode rejection ratio (CMRR). The neural signals with small amplitude can be easily contaminated by large-amplitude common-mode (CM) interferences due to the degraded CMRR. This brief presents a CMRR enhancement circuit for the CCIA, with which the capacitor mismatches can be compensated in a power-efficient manner. In the proposed CCIA, the gains of a pair of output stages are controlled separately to reject the output signals generated by the CM interferers in the presence of capacitor mismatches. Employing the proposed CMRR enhancement scheme, the implemented CCIA achieves a CMRR over 90 dB from 10 Hz to 1 kHz and 3.4- $\mu \text{V}_{\mathrm{ rms}}$ integrated input-referred noise (IRN) while only consuming $1.5~\mu \text{W}$ per channel.

Capacitively Coupled Instrumentation amplifier with optimized feedback pseudo-resistor for wet-gel based electrodes

Different types of electrodes are used for stable monitoring of physiological signals. Commonly used Silver-silver chloride (Ag/AgCl) metal gel-based electrodes and gold metal electrodes used for ECG and EEG respectively introduce substantial noise component and offer very high contact impedance to the subsequent amplifier. A Capacitively Coupled Instrumentation Amplifier (CCIA) is extensively used for low noise amplification of the acquired bio-potential signal. Amplification of low-frequency bio-potential signals while discarding the DC-offset requires a distinct low-frequency high-pass pole, which is implemented using pseudo-resistors in feedback of CCIA. However, pseudo-resistors exhibit the non-linearity due to large voltage swing at the output. This also makes the high-pass pole of the system time-variable. In this paper, different structures of non-tunable and tunable pseudo-resistor are simulated using Cadence spectre simulator with 0.18 µm technology. The structures having equivalent resistance ∼1 TΩ over ±1 V range are the employed across the feedback of current mirror based CCIA. The simulation results show the improvement in the lower cut-off frequency and performance metrics of CCIA using different pseudo-resistor structures.

A design of readout IC with capacitively-coupled chopper current-feedback instrumentation amplifier in a 0.18 μm CMOS process

This paper describes a readout IC (ROIC), which consists of a capacitively coupled instrumentation amplifier (CCIA) and a discrete-time delta–sigma modulator. An active high-pass filter is embedded in the ripple reduction loop to suppress the noise ripple amplitude due to chop modulation. To accommodate the input with large electrode offset, dc-servo loop (DSL) and a 6 bit capacitive DAC are employed to suppress large electrode offset, while a positive feedback loop to boost its input impedance. The complete CCIA is implemented in a standard 0.18 μm 1P6M CMOS process. It occupies an area of 0.56 mm2 (including DSL) and consumes 52 μA current from a 3.3 V supply voltage. Measurement results indicate that the input reference noise PSD is 53.8 nV√Hz.

A 22-bit Read-Out IC With 7-ppm INL and Sub-100-$\mu$ Hz 1/$f$ Corner for DC Measurement Systems

A 22-bit read-out integrated circuit (IC) is constructed from a capacitively coupled instrumentation amplifier (CCIA) followed by an incremental delta-sigma ( $\Delta \Sigma $ ) analog-to-digital converter (ADC), both of which have programmable gain. The CCIA has a cascode Miller-compensated differential difference amplifier (DDA) with clamp transistors for energy efficiency. The offset and 1/ $f$ noise of the fully differential read-out IC are suppressed by chopping and correlated double sampling (CDS) techniques, which are synchronized with sampling by the ADC. Residual low-frequency noise is reduced by the second-order system-level chopping technique with an on-chip moving-averaged finite impulse response (FIR) filter. Implemented in a standard 0.13- $\mu \text{m}$ CMOS process, the read-out IC achieves a maximum effective resolution (ER) of 21.9 bit, an integral nonlinearity (INL) of 7 ppm, and a 1/ $f$ corner of 40 $\mu $ Hz. The chip draws only 142 $\mu \text{A}$ from 3-V supply and 18 $\mu \text{A}$ from the 1.5-V supply, and it has an active area of 0.65 mm2 including digital filter.

An Energy-Efficient 3.7-nV/&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\surd$ &lt;/tex-math&gt; &lt;/inline-formula&gt;Hz Bridge Readout IC With a Stable Bridge Offset Compensation Scheme

This paper describes an energy-efficient bridge readout IC (ROIC), which consists of a capacitively coupled instrumentation amplifier (CCIA) that drives a continuous-time delta–sigma modulator (CT $\Delta \Sigma \text{M}$ ). By exploiting the CCIA’s ability to block dc common-mode voltages, the bridge’s bias voltage may exceed the ROIC’s supply voltage, allowing these voltages to be independently optimized. Since bridge output is typically much smaller than bridge offset, a digital to analog converter (DAC) is used to compensate this offset before amplification and thus increase the CCIA’s useful dynamic range. Bridge loading is reduced by using a dual-path positive feedback scheme to boost the CCIA’s input impedance. Furthermore, the CCIA’s output is gated to avoid digitizing its output spikes, which would otherwise limit the ROIC’s linearity and stability. The ROIC achieves an input-referred noise density of 3.7 nV/ $\surd $ Hz, a noise efficiency factor (NEF) of 5, and a power efficiency factor (PEF) of 44, which both represent the state of the art. A pressure sensing system, built with the ROIC and a differential pressure sensor (AC4010), achieves 10.1-mPa ( $1\sigma$ ) resolution in a 0.5-ms conversion time. The ROIC dissipates about 30% of the system’s power dissipation and contributes about 6% of its noise power. To reduce the sensor’s offset drift, a temperature compensation scheme based on an external reference resistor is used. After a two-point calibration, this scheme reduces bridge offset drift by $80\times $ over a 50 °C range.

Self-Biased Ultralow Power Current-Reused Neural Amplifier With On-Chip Analog Spike Detections

An ultralow power 0.6 V neural amplifier with on-chip analog spike detection is presented. A capacitively-coupled instrumentation amplifier (CCIA) with the current-reused and self-biased scheme is proposed to reduce the overall power consumption and to enhance the noise efficiency. The transistors in the amplifier are operated in the subthreshold region to enhance noise performance. The analog-domain spike detection based on a low power peak detector can reduce the overall power consumption. The circuit is fabricated using the standard 0.18 μm CMOS process. The passband of the circuit is from 6.4 Hz to 4.46 kHz. Input-referred noise is 10.68 μVrms. The supply voltage is 0.6 V, and the power consumption of the singlestage CCIA is 50.6 nW. The CCIA achieves a good noise efficiency factor and power efficiency factor of 1.79 and 1.93, respectively. The overall power consumption including two CCIAs, the programmable gain amplifier, and the analog spike detector is 269.8 nW. Input spikes with an amplitude of 50 μV at 100-Hz intervals are accurately detected.

A 2- 45-nV/√Hz Readout Front End With Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop

This brief presents an ultra-low-power low-noise chopped capacitively coupled instrumentation amplifier (CCIA) that is suitable for neural recording applications. An active high-pass filter is embedded in the ripple reduction loop (RRL) to suppress the residual noise and relax the capacitor size. Multiple chopping is employed to further reduce the residual output ripple due to the RRL offsets. A dc servo loop (DSL) using a 14-nA pseudofeedback amplifier is proposed to achieve a subhertz high-pass corner while using only a 15-pF on-chip capacitor. The complete CCIA is implemented in a standard 0.18- $\mu\text{m}$ CMOS process. It occupies an area of 0.23 mm2 (including the DSL) and consumes 1.7 $\mu\text{A}$ from a 1.25-V supply, achieving a noise efficiency factor of 2.9 that compares favorably with the state of the art.