A 22-bit Read-Out IC With 7-ppm INL and Sub-100-$\mu$ Hz 1/$f$ Corner for DC Measurement Systems

Abstract

A 22-bit read-out integrated circuit (IC) is constructed from a capacitively coupled instrumentation amplifier (CCIA) followed by an incremental delta-sigma ( $\Delta \Sigma $ ) analog-to-digital converter (ADC), both of which have programmable gain. The CCIA has a cascode Miller-compensated differential difference amplifier (DDA) with clamp transistors for energy efficiency. The offset and 1/ $f$ noise of the fully differential read-out IC are suppressed by chopping and correlated double sampling (CDS) techniques, which are synchronized with sampling by the ADC. Residual low-frequency noise is reduced by the second-order system-level chopping technique with an on-chip moving-averaged finite impulse response (FIR) filter. Implemented in a standard 0.13- $\mu \text{m}$ CMOS process, the read-out IC achieves a maximum effective resolution (ER) of 21.9 bit, an integral nonlinearity (INL) of 7 ppm, and a 1/ $f$ corner of 40 $\mu $ Hz. The chip draws only 142 $\mu \text{A}$ from 3-V supply and 18 $\mu \text{A}$ from the 1.5-V supply, and it has an active area of 0.65 mm2 including digital filter.