Cadence Tool Research Articles

Enhancement in Retention Time of 3TDRAM Using Double Gate Finfet Technology at Nanometer Regime.

Leakage current, power and area is the key challenges for VLSI designer during implementation of low power devices. In an integrated circuit number of transistors double in small silicon area every two years. There are certain limitations of cmos technology in nanometer regime out of which leakage current, leakage power, average current and average power is an important issues. In this paper, Retention time improvement in three transistor dynamic random access memory using double gate Finfet technology is proposed. Double gate finfet technology in 3TDRAM overcomes the issues related to cmos technology and it does not required additional circuitry. Proposed 3T DRAM is investigated with cmos and finfet technology at 90nm technology using cadence tool. Analysis of 3TDRAM using cmos and double gate finfet technology is carried out by variation in supply voltage and capacitance values. In double gate finfet technology leakage parameters are minimized and retention time(Th) is more improved as compared to cmos technology is observed.

Dual mode Bluetooth Controller via PCM-CODEC Interface for Audio Application

Bluetooth may be an inaccessible development standard utilized for exchanging data between settled and flexible contraptions over brief divisions utilizing UHF radio waves within the mechanical, coherent, and restorative radio bunches, from 2.402GHz to 2.480 GHz. PCM codec is an A/D interface for speech signals. The Bluetooth center framework underpins co-ordinate transport of application information that’s isochronous and of a consistent rate (either bit-rate or frame-rate for pre-framed information) employing an SCO or ESCO consistent joins. These coherent joins save physical channel transfer speed and give a consistent rate of transport bolted to the piconet clock. The codec interface block is used to interface an external PCM (8KHz voice data) or a stereo codec with the baseband controller for the direct transfer of voice data on isochronous links to external CODEC. Bluetooth baseband supports two CODEC interface protocols 1) for audio links it is the PCM interface and 2) for mono/stereo music data from audio codec it uses the IIS interface. This enables the source of isochronous data to be directly interfaced to the baseband controller if it is not required to be processed by firmware. It also provides the host access path where the source of isochronous data will be any application running on the host and data is written and read directly into baseband SCO/ESCO FIFOs from firmware. In this paper, PCM is verified in the Cadence tool and simulated images are shown.

Ultra Low Frequency Wide Band Low Pass Active Filter for Bio-Medical Applications Simulated on Cadence tool

An ultra low frequency wide band low pass active filter is designed and simulated on 180nm cadence virtuoso tool for biomedical applications in this paper. This proposed designed low pass active filter is being able to stop low frequency signal of µHz and can pass up to Hz using the CMOS nanotechnology. This is a second order low pass active filter. It can be useful to identify the human disease by detecting ultra low frequency bio-signal. The simulated result shows ultra low power consumption of 200pW with high bandwidth at 1mV input supply.

Area and power delay product efficient level restored hybrid full adder (LR-HFA)

Full adder circuit is a ubiquitous building block in VLSI systems and application specific integrated circuits. This article presents an area and power delay product (PDP) efficient CMOS based 1 bit full adder which is suitable to perform arithmetic operations. The simulation results obtained for parameter analysis using Cadence tool shows that the proposed adder preserves more than 20.7% power over the conventional CMOS adder. The PDP is reduced by almost 26.8–55.5% and performs 9.8–46.1% faster operation than the existing adders. The proposed design is investigated in terms of variations in supply voltage, load capacitance, process corner and temperature. To evaluate the performance of LR-HFA in real time environment, we embedded it in a 4, 8, 16 bit carry propagation adder. The proposed adder displays improved PDP performance when compared with standard adder circuits.

Fully-integrated DCDC buck converter based on PID algorithm

With the continuous development of power supply technology, the application of power management chips becomes more extensive, and the requirements for fully integrated power management chips are getting higher. This paper designs a buck converter with a fully integrated digital control circuit and power circuit with an output voltage of 2V. In voltage mode, digital pulse width modulation (DPWM) technology and PID algorithm are used, and a digital closed-loop control buck circuit system is designed by cadence tools. The performance of analog and digital closed-loop control circuits is compared at the same buck power stage. Under rated load conditions, the lock-up time of the digital control buck circuit is 826us, the output voltage ripple is 14.75mV, the response time of load sudden change at light load is about 900us, and the response time of load sudden change at heavy load is about 2ms.

WITHDRAWN: Implementation of low power one bit full adder with cadence tool

Abstract In this research paper, the one-bit low power hybrid adder circuit is developed by additional logic of direct polarization and the reverse polarization method (FSB / RSB) of the Complementary metal-oxidesemiconductor (CMOS) and Transmission Gate Logic (TGL). A full adder of 1-bit is proposed in 180 nm technology and the performance parameters, such as delays, strengths, and areas, are compared to such as CMOS, 10 T, 14 T, and Hybrid Connectors. The design uses a power supply of 1.8 V for 180 nm technology. Compared to other existing full additive designs, there is a better improvement in the strength of the proposed adder and PDP reference.

Efficient Hardware Implementation of Pseudo-Random Bit Generator Using Dual-CLCG Method

In this work, the architecture of a dual-coupled linear congruential generator (dual-CLCG) for pseudo-random bit generation is proposed to improve the speed of the generator and minimize power dissipation with the optimum chip area. To improve its performance, a new pseudo-random bit generator (PRBG) employing two-operand modulo adder and without shifting operation-based dual-CLCG architecture is proposed. The novelty of the proposed dual-CLCG architecture is the designing of LCG based on two-operand modulo adder rather than a three-operand one and without using shifting operation as compared to the existing LCG architecture. The aim of the work is to generate pseudo-random bits at a uniform clock rate at the maximum clock frequency and achieve maximum length of the random bit sequence. The power dissipation with the optimum chip area of PRBG is also observed for the proposed architecture. The generated sequence passes all the 15 tests of the National Institute of Standards and Technology (NIST) standard. Verilog HDL code is used for the design of the proposed architecture. Its simulation is done on commercially available Spartan-3E FPGA (ISE Design Suite by Xilinx) as well as on 90-nm CMOS technology (Cadence tool).

A high-speed 4-bit Carry Look-Ahead architecture as a building block for wide word-length Carry-Select Adder

A 4-bit Carry Look-Ahead (CLA) architecture for carry-generation process is proposed. CLA architecture proposed in this work uses complex CLA circuits for carry-generation rather than using carry-generate and carry-propagate functions which are used in the conventional process of 4-bit CLA architecture. Performance of the proposed CLA architecture is validated by performing simulation utilizing Cadence tools in standard 45 ​nm CMOS process. In order to prove effectiveness, performance of the proposed 4-bit CLA design is compared with existing 4-bit CLA designs. Moreover, as a possible application of the proposed design and to inspect performance in wide word length adder structure, the 4-bit CLA architectures (proposed and existing) are extended to 16-bits using Carry-Select Adder (CSA) architecture. Both as 4-bit cell and extended 16-bit structure, the proposed 4-bit CLA shows remarkable improvement in speed while maintaining quite acceptable level of power consumption. As a result, the proposed 4-bit CLA can be utilized as a highly suitable substitution of the existing 4-bit CLA architectures in high-speed microprocessor design.

Dual-scan architecture for 2D discrete wavelet transform using modified lifting algorithm

An efficient architecture of discrete wavelet transform (DWT) in two-dimension (2D) is presented in this paper. The proposed structure has a higher hardware efficiency and better performance than the other DWT structures. The conventional lifting scheme is modified to reduce the latency and critical path to one multiplier delay (1Tm). The processing speed of the architecture is increased by introducing four pipeline stages in the DWT structure. Cohen-Daubechies-Feauveau (CDF) 9/7 wavelet filter is implemented in the paper. The data scanning of the input image for processing is done in Z-fashion. The computation time of an N × N image is N2/2 and the temporal buffer requirement is 4N. The DWT architecture developed based on the modified lifting scheme has a regular data flow with a throughput rate of two. Very high speed hardware description language (VHDL) is used to describe the digital design. The architecture is implemented on CADENCE tool with CMOS 180 nm technology. The results after comparison indicate that the proposed architecture is hardware efficient and memory utilisation is reasonable as a result of which this structure can be used in real-time image and video compression.

Footer Voltage Controlled Dual Keeper Domino Logic with Static Switching Approach

In this paper, two circuits, namely Footer Voltage Controlled Dual Keeper domino logic (FVCDK) and Footer Voltage Controlled Dual Keeper with Static Switching domino logic (FVCDK-SS) are presented, in order to achieve high speed, low power consumption and robustness. The dual keeper arrangement helps in reducing the loop gain of the feedback circuitry, which leads to lower delay variability. The keeper circuitry is controlled using the footer voltage to reduce the contention current in the initial evaluation phase, and thus providing enhanced speed. In FVCDK-SS domino logic, unwanted transients at the output are reduced by incorporating pseudo-dynamic buffer in the proposed FVCDK domino logic. This further reduces the dynamic power consumption. The results of the logic presented here are validated by comparing them to a wide range of existing domino logic circuits for a~variety of performance metrics such as delay, power, power-delay product and unity noise gain. To effectively gauge the wide fan-in capabilities of the proposed logic, results are shown for the various fan-in OR gate. The simulations of the circuits are carried out using industry standard full-suite Cadence tools using 45~nm technology library.

A New Model of Dynamic Logic Circuit with NMOS based Keeper

Abstract Dynamic logic circuits are widely popular due to a smaller number of transistors and consume less area. But the time to switch between logics is higher due to higher contention value. A new model of the logic using nMOS based keeper circuit is proposed and the performance is evaluated using Cadence tools. Comparative results demonstrate the suitability and competency of the proposed circuit.

A Novel Low Power Technique for FinFET Domino OR Logic

Excessive scaling of complementary metal oxide semiconductor (CMOS) technology is the main reason of large power dissipation in electronic circuits. Very large-scale integration (VLSI) industry has chosen an alternative option known as fin-shaped field effect transistor (FinFET) technology to mitigate the large power dissipation. FinFET is a multi-gate transistor which dissipates less leakage power as compared to CMOS transistors, but it does not completely resolve the problem of power dissipation. So, leakage reduction approaches are always required to mitigate the impact of power dissipation. In this paper, cascaded leakage control transistors (CLCT) leakage reduction technique is proposed using FinFET transistors. CLCT approach is tested for basic static logic circuits like inverter, 2-input NAND and NOR gates and compared with the existing leakage reduction techniques for leakage power dissipation and delay calculations at 16 and 14 nm technology nodes using Cadence tools. CLCT approach shows the effective reduction of leakage power with minimum delay penalty. As the domino logic gates are widely used in large memories and high-speed processors therefore, CLCT approach is further utilized for footless domino logic (FLDL) and compared with the available methods at 14[Formula: see text]nm technology node. CLCT approach reduces 35.16% power dissipation as compared to the conventional domino OR logic. Temperature and multiple parallel fin variations are estimated for the domino OR logic to check its reliable operation. CLCT approach has high-noise tolerance capability in term of unity noise gain (UNG) for domino OR logic as compared to the other methods.

An Efficient Architecture for Modified Lifting-Based Discrete Wavelet Transform

A high speed and memory efficient lifting based architecture for one-dimensional (1-D) and two-dimensional (2-D) discrete wavelet transform (DWT) is proposed in this paper. The lifting algorithm is modified in this work to achieve a critical path of one multiplier delay with minimum pipeline registers. A 1-D DWT structure with two-input/two-output and four-input/four-output is developed based on the modified lifting scheme. The proposed 2-D DWT architecture for the Daubechies 5/3 and 9/7 filter comprises of two 1-D processors, together with a transpose and a temporal memory. An efficient transpose block is presented, which utilizes three registers to transpose the output sequence of the 1-D DWT block. The transpose block is independent of the size of the image read for the transform. The scanning process of an $$N \times N$$ image for a one-level 2-D transform is in Z fashion to minimize the temporal buffer to 4N and 2N for the 9/7 and 5/3 mode DWT respectively. The comparison results show that the proposed structure is hardware cost-effective and memory efficient, which is favorable for real-time visual operations. The model is described in VHDL and synthesized using the Cadence tool in 90 nm technology.

Reconfigurable Wide Input Range, Fully-Differential Indirect Current-Feedback Instrumentation Amplifier with Digital Offset Calibration for Self-X Measurement Systems

Abstract This manuscript presents an implementation of the configurable indirect current-feedback instrumentation amplifier (CFIA) for sensor interface readout circuit. Configuration is achieved by designing digital weighted scalable arrays for some selected elements to serve as tuning knobs controlled by the evolutionary optimization algorithm. This scheme resulting in a programmable circuit for different aspects to support self-x functionality. The robustness and flexibility of the proposed circuit fit to the demands of measurement and sensory systems in industry 4.0 and other intelligent systems applications. The circuit is designed by Cadence tools using ams 0.35 μm CMOS technology.

SBOX under PVT variation

The process corner refers to the variation into fabrication parameters used to apply during integrated circuit design to the semiconductor wafer. Inconsistency during design and deviation of voltage and temperature during its operation widens the worst-case margin and significantly degrades the performance. The impact of variation is more pronounced at smaller technology node (< 90 nm). In CAD-tool variability are modeled as fast and slow MOS transistors. Design parameters must be validated at all corners before sending them to be fabricated. In this work, the schematic of the substitution box (SBOX) implemented with the cadence tool at CMOS 45 nm technology node and their variability analyzed. The impact of variation onto the SBOX parameter (power, delay, and energy) has presented at process corners with ± 10% variation in supply voltage and temperature (27–80 °C). The simulation result shows that the best choice of SBOX implementation when NMOS tends to get fast and PMOS tends to get slow.

Design of optimal high-frequency CMOS VCOs for automotive application

In this paper, a design methodology of Voltage-Controlled Oscillator (VCO) for long-range automotive RAdio Detection And Ranging (RADAR) is proposed and simulation analysis is carried out over Virtuoso SpectreRF software on Cadence tool. The frequency ranges of the mm-wave CMOS current-starved ring and LC VCOs for 45-nm CMOS technology are 24 and 76 GHz, respectively. The ring VCO at 25 GHz oscillation frequency demonstrates 2.06% tuning range, phase noise −71.61 dBc/Hz at 1-MHz offset, 3.43 mW power dissipation and layout area of $$20\times 20 \,\upmu {\mathrm{m}}^2$$ whereas cross-coupled LC VCO achieves an oscillation frequency of 76.25 GHz for frequency tuning range of 0.65%, a phase noise of −92.44 dBc/Hz at 1-MHz offset, 8.59 mW power dissipation and $$320\times 320 \,\upmu {\mathrm{m}}^2$$ layout area. The proposed design of efficient VCOs shows an excellent performance for long-range automotive RADAR.

Second Order Low Pass RC Active Filter for Low Frequency Signal Processing

The different parameters define the characteristics of filter for various applications like: Biomedical applications, Defense communication systems, Wireless Communication systems etc. The mostly measured parameters for filter designing are frequency range, cut off frequency, gain, power consumption, and noise. In this paper, our work focuses on frequency range measurement at cut off frequency of Hz of second order low pass filter with designed using CMOS technology for IC fabrication. The proposed circuit gives the high frequency range at low frequency (100Hz – 10MHz) with 1mV 50Hz low power supply using complementary compound pair on the value of R=1K and C=10pH. This second order active low pass filter provides high amplification at the output with 4.861V. It is implemented and simulated on 180nm Cadence tool in terms of wide frequency range or band at cut off frequency of Hz to MHz.

Design of area efficient VLSI architecture for carry select adder using logic optimization technique

AbstractSquare Root Carry Select Adder (SQRT‐CSLA) is accomplishing the noteworthy attention in the arena of VLSI (Very‐Large‐Scale Integration) systems as it can process the computations with high speed. Though the current trending SQRT‐CSLA adder designing techniques are effective in various performance metrics, there is a possibility to improve the design addressing various performance metrics. This article proposes CSLA architecture by employing Zero Finding Logic using the Logic optimization technique (ZFCLOT). CSLA using ZFCLOT is designed, simulated, and synthesized using 90 nm cadence tools. CSLA using ZFCLOT achieves an area efficiency of 46.127% and a power efficiency of 48.4% as against to SQRT‐CSLA.

Design and Implementation of Vlsi Architecture for Arrhythmia Detection

Arrhythmia is one in all the foremost well-liked heart diseases that might result in serious consequences. In case of arrhythmia, the heart rate may be either too fast or slow. When a person suffers from arrhythmic the heart may not pump sufficient blood to all body parts that is necessary for circulation. some of the symptoms of arrhythmia includes faintness ,fluttering your chest, a light headedness or dizziness, fainting or near fainting and on the worst it may turn out to be deadly causing ventricular fibrillation. Due to this it is very crutial to detect conditions of arrhythmia. It is very difficult to identify the symptoms of arrhythmia from a long ECG record. This projects presents a VLSI based design of high speed and minimum area for arrhythmia detection .It uses arithmetic distribution discrete wavelet transform for arrhythmia detection of QRS wave and is implemented using CADENCE. The purpose of distributive arithmetic discrete wavelet change is to compress the ECG signal. ECG signals are generated via MATLAB. The resultant of these coefficients are given to the LUT, which comprises of MIT-BIH databases. Our aim is to detect the QRS complex in the ECG signal and to identify the time and frequency variations. By comparing these variations with that of the reference variations produced in the normal ECG waveform it is easy to identify whether the patient is suffering from arrhythmia or not. The coding was written in verilog and stimulated in modelsim software and implemented using CADENCE tool.

Low Power FPGA Implementation of Multi-View Video Coding with Hybrid Compression and Decompression Algorithm

The video is one of the most useful and most appealing medium to represent some information. More usage of digital multi-media via communications media, wireless communications, intranet, internet and cellular mobile leads to the uncontrollable growth of data in media. The video compression technique is used in this research work to improve the processing speed of the entire system. In this work, Low Cost - Multi Video Coding - Hybrid Compression and Decompression (LC-MVC-HCD) method is used to reduce computation complexity. The combinational of Discrete Wavelet Transform (DWT) and Discrete Cosine Transform (DCT) algorithms are denoted as hybrid algorithm. Based on this hybrid algorithm, the compression process is performing which improves the video coding efficiency of MVC. The LC-MVC-HCD methodwas implemented in the Matlab, Xilinx and Cadence tool. In Application Specific Integrated Circuit (ASIC) implementation, the area, power, and delay minimized by using the cadence encounter tool with 180nm and 45nm technology. In Field Programmable Gate Array (FPGA) implementation, the number of Lookup Tables (LUTs), slice, and flip-flop are minimized based on two different kinds of Virtex devices such as Virtex -6 and Virtex-7. In Matlab, Peak Signal to Noise Ratio (PSNR), computational time and bit error rate were analyzed for the LC-MVC-HCD method. The experimental outcome showed that the proposed methodology has improved performance ASIC and FPGA up to 2-3% compared to existing methods like Direct mode decision MVC and LC-MVC-DWT.