SBOX under PVT variation

Abstract

The process corner refers to the variation into fabrication parameters used to apply during integrated circuit design to the semiconductor wafer. Inconsistency during design and deviation of voltage and temperature during its operation widens the worst-case margin and significantly degrades the performance. The impact of variation is more pronounced at smaller technology node (< 90 nm). In CAD-tool variability are modeled as fast and slow MOS transistors. Design parameters must be validated at all corners before sending them to be fabricated. In this work, the schematic of the substitution box (SBOX) implemented with the cadence tool at CMOS 45 nm technology node and their variability analyzed. The impact of variation onto the SBOX parameter (power, delay, and energy) has presented at process corners with ± 10% variation in supply voltage and temperature (27–80 °C). The simulation result shows that the best choice of SBOX implementation when NMOS tends to get fast and PMOS tends to get slow.