Cadence Tool Research Articles

Design of 10 Bit ADC of SAR Type to Increase the Accuracy for Biomedical Applications

In this paper a low power consuming 10 bit SAR ADC which is suitable for Biomedical applications is presented. It was designed with 180nm technology using cadence tool. SAR ADC is made of dynamic comparator, sample and hold circuit, SAR logic, and DAC block. The designed circuit works on a supply voltage of 1V. The proposed SAR design, with the use of dynamic comparator circuit will help to reduce power and even at the same time with the use of binary weighted CDAC also provides low power dissipation. In order to decide the next significant bit by the knowledge of previous bits the successive approximation algorithm runs over several clock cycles for analog to digital conversion. Power usage and complexity of the circuit is minimized by low conversion rate i.e permitting one clock for each bit in the proposed method.

Device and Circuit-Level Assessment of GaSb/Si Heterojunction Vertical Tunnel-FET for Low-Power Applications

This article investigates the performance of a vertically grown GaSb/Si tunnel field effect transistor (V-TFET) with a source pocket to enhance the performance of the device. The commercially available Silvaco TCAD has been used for simulating the proposed V-TFET structure. A low bandgap material, GaSb, is used in the source region for the first time to enhance the carrier tunneling through the source (GaSb)-channel (Si) heterojunction. The proposed V-TFET with a pocket shows the improved subthreshold swing (SS) of 26 mV/decade at ${V}_{{\textit {DS}}}= 0.5$ V over the V-TFET without any pocket. The effects of temperature on SS and ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio along with the analog/RF figures of merit (FOMs) are also analyzed for V-TFETs with and without a pocket. The results are also compared with some recently reported TFETs. The dc and analog/RF performances of V-TFET with a pocket are shown to be better than those of the V-TFET without a pocket and other reported TFET structures. Finally, the applications of V-TFETs with and without a pocket in designing inverter and ring oscillator circuits have been demonstrated. The dc and transient responses of the V-FET-based inverter and ring oscillator circuits have been analyzed using the Verilog-A model in the CADENCE tool.

Physical IC Design Layout of Memory-Based Real Fast Fourier Transform Architecture using 90nm Technology

In this paper we present a low complexity physical IC layout for memory based Real Fast Fourier Transform (RFFT) architecture using 90nm technology. FFT architectures are the most important algorithms in the modern communication systems like and very high bit rate digital subscriber line (VDSL) asymmetric digital subscriber line (ADSL). In this FFT algorithm is based on radix-2 decimation-in-frequency. In order to meet the real time requirements of very large scale integration (VLSI), we designed a low complexity and high speed FFT architecture. The RFFT architecture was realised using Verilog hardware description language (HDL). This architecture is simulated using Native code launch of cadence and synthesized using RTL code complier of cadence tool. Each step of application specific integrated circuit (ASIC) physical IC design flow was synthesized using cadence Innovus 90nm technology and we optimize the design to reduce the area, power and timing requirements.

Design of a good oscillation frequency and moderate phase noise current mirror VCO

Abstract This brief presents a good oscillation frequency and moderate phase noise voltage controlled oscillator (VCO) using current mirror topology. Here, a novel VCO using current mirror is designed which increases current in the cross-coupled circuit hence the single-ended output voltage. The width of mirroring transistors is decreased so that the current gain is increased in each branch of differential configuration. It leads to increase in single-ended drain current. Therefore, the close-in phase noise settlement from the enhanced voltage variation at the VCO output due to enhanced current flow in the circuit. The proposed VCO architecture is implemented in 180 nm CMOS process and simulated in Cadence tool. It demonstrates the tuning range of 2.165 to 2.235 GHz and a lower phase noise of -112 dBc/Hz at carrier offset of 1 MHz and -30 dBc/Hz at carrier offset of 1 KHz with a power consumption of 6.71 mW. So, this work will be a proper building block for the design of a customized receiver.

A Novel high-speed low power 9T full adder

In modern era, low power high speed applications become one of the prime areas of focus for digital VLSI applications. Addition is a vital arithmetic operation and it acts as the main building block for synthesizing all other operations. A low power high speed full adder is introduced using 9 transistors. It consists of 3 modules, XOR module, sum module and carry module. While comparing with other designs it has a significant reduction in delay, power and hence the power delay product. The circuit is implemented and simulated using Cadence Virtuoso tool. Entire design is divided into three modules. Module 1 consists of modified XOR circuit which has only four transistors. Module 2 and Module 3 are SUM and CARRY design respectively. CARRY OUT of full adder circuit is made up by using Gate Diffusion Input (GDI)logic whereas the SUM is made using another XOR design. The design was implemented using cadence tool and power, delay and PDP are found to be very small as compared with otherdesigns.

Design of fault tolerant majority voter for error resilient TMR targeting micro to nano scale logic

The shrinking size of transistors for satisfying the increasing demand for higher density and low power has made the VLSI circuits more vulnerable to faults. Therefore, new circuits in advanced VLSI technology have forced designers to use fault tolerant techniques in safety-critical applications. Also, the presence of some faults (not permanent) due to the complexity of the nanocircuit or its interaction with software results in malfunctioning of circuits. The fault tolerant scheme, where majority voter plays the core role in triple modular redundancy (TMR), is being implemented increasingly in digital systems. This work targets to implement a different fault tolerant scheme of majority voter for the implementation of TMR using quantum-dot cellular automata (QCA), viable alternative nanotechnology to CMOS VLSI. The fault masking ability of various voter designs has been analysed in details. The fault masking ratio of the proposed voter (FMV) is 66% considering single/multiple faults. Simulation results establish the validation of proposed logic in QCA which targets nano-scale devices. The proposed logic is also suitable for conventional CMOS technology, which is verified with the Cadence tool.

Design of fault tolerant majority voter for error resilient TMR targeting micro to nano scale logic

The shrinking size of transistors for satisfying the increasing demand for higher density and low power has made the VLSI circuits more vulnerable to faults. Therefore, new circuits in advanced VLSI technology have forced designers to use fault tolerant techniques in safety-critical applications. Also, the presence of some faults (not permanent) due to the complexity of the nanocircuit or its interaction with software results in malfunctioning of circuits. The fault tolerant scheme, where majority voter plays the core role in triple modular redundancy (TMR), is being implemented increasingly in digital systems. This work targets to implement a different fault tolerant scheme of majority voter for the implementation of TMR using quantum-dot cellular automata (QCA), viable alternative nanotechnology to CMOS VLSI. The fault masking ability of various voter designs has been analysed in details. The fault masking ratio of the proposed voter (FMV) is 66% considering single/multiple faults. Simulation results establish the validation of proposed logic in QCA which targets nano-scale devices. The proposed logic is also suitable for conventional CMOS technology, which is verified with the Cadence tool.

Implementation of full Adder with 2x1 Mux using Optimised Gdi Technique

The major considerations of any digital circuit are area and power consumption. GDI (Gate Diffusion Input) - an advanced technique is proposed for designing a circuit in order to reach the requirements, reduce power consumption, and effective utilization of area. Despite having many uses, the GDI technique is noted for some drawbacks. The principle point of this paper is to concentrate on the downsides of the existing GDI technique and to propose an improved version of GDI technique to withstand the disadvantages of the earlier one. A full adder with 2x1 MUX is designed using conventional techniques and compared their simulation results with full adder using optimized GDI technique. Simulation and analysis of the full adder are carried out using CADENCE tool at 45nm technology. Simulation results proved that the proposed design had improved the performance of GDI and reduces almost less than 50% of layout area and power consumption is only 1.5% of the power consumed using conventional technique.

A High Performance Early Acknowledged Asynchronous Pipeline using Hybrid-logic Encoding

This paper details a novel asynchronous pipelining methodology that maximizes the throughput buffering capacity and robustness of gate-level pipelined systems. The data paths in the proposed pipeline style are encoded using hybrid logic encoding scheme, which incorporates simplicity of the single-rail encoding and robustness of the dual-rail encoding. The control path that provides the synchronization between pipeline stages is constructed based on the simple and high-speed early acknowledgment protocol. Further, the proposed pipeline accommodates isolate phase to achieve 100% storage capacity. Two test cases: A 4-bit,10-stage FIFO and a 16-bit adder, have been designed in 90 nm technology to validate the proposed pipeline style. The FIFO has been laid out in the UMC 180 nm process using the cadence tool suite. The post-layout results of FIFO show 12.5% better throughput than the high capacity single-rail pipeline. Simulation results of the adder also reveal that the proposed structure achieves the throughput of 3.44 Giga-items/sec, which is 44.18% higher than the APCDP (Asynchronous pipeline based on constructed critical path) and 11.9% higher than the high capacity single-rail pipelines.

VLSI implementation of an area and energy efficient FFT/IFFT core for MIMO-OFDM applications

This research article presents an implementation of high-performance Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) core for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM)-based applications. The radix-2 butterflies are implemented using arithmetic optimization technique which reduces the number of complex multipliers involved. High-performance approximate multipliers with negligible error rate are used to eliminate the power-consuming complex multipliers in the radix-2 butterflies. The FFT/IFFT prototype using the proposed high-performance butterflies are implemented using Altera Quartus EP2C35F672C6 Field Programmable Gate Array (FPGA) which yields 40% of improved logic utilization, 33% of improved timing parameters, and 14% of improved throughput rate. The proposed optimized radix-2-based FFT/IFFT core was also implemented in 45-nm CMOS technology library, using Cadence tools, which occupies an area of 143.135 mm2 and consumes a power of 9.10 mW with a maximum throughput of 48.44 Gbps. Similarly, the high-performance approximate complex multiplier-based optimized FFT/IFFT core occupies an area of 64.811 mm2 and consumes a power of 6.18 mW with a maximum throughput of 76.44 Gbps.

A 2.4 GHz double balanced downconversion mixer with improved conversion gain in 180-nm technology

In this paper a 2.4-GHz non-return to zero (abbreviated as NRZ) active downconversion mixer for transceiver system is demonstrated. It features with the double- balanced topology, NRZ mechanism, an effecting biasing technique and a current mirror technique are used to achieve the requirements. Downconversion mixer is realized on 180 nm CMOS technology. Despite of trade-off between conversion gain and linearity we can achieve very high conversion gain with moderate linearity. Simulations using cadence tool exhibits a conversion gain of 24.61 dB, a third order intercept point of 6.17 dB, a 1-dB compression point of − 5.86 dB and a second order intercept point of + 87.66 dB at 1.8 V supply.

Design of an Area-Efficient Various N-point Support radix-2/22 FFT using Modified Butterfly Units

Fast Fourier Transform (FFT) acts as an element in the high-speed signal processing application, which involves the following subsequent operations, namely complex addition, complex subtraction and complex multiplication. Due to the complex multiplication operation, the FFT structures lead to more hardware demand. Hence, this work introduces an area-efficient various N-point support radix-2 and radix-22 FFT structure by using proposed modified butterfly units and radix-2/22 butterfly unit. The proposed modified butterfly units are used to reduce the number of complex multipliers effectively. For this reason, it is using for certain conditions in FFT design instead of existing radix-2/22 butterfly unit. Further, the proposed design supported to perform various size of FFT in a single architecture without increasing the extra element demand. Moreover, the proposed FFT structure designed and implemented using a Xilinx Virtex-6 Field-Programmable Gate Array (FPGA) device (6vcx75tff484-2) and Cadence tool with 45nm CMOS technology. The implementation results demonstrate that the proposed N-point (N=16, 32 and 64) DIF-FFT design attains the less hardware complexity when compared with existing multi-mode FFT design. Then the proposed area-efficient 16-point, 32-point and 64-point radix-2 FFT architectures reduce the total area by 20.99%, 11% and 4.9% respectively. As well, the proposed area-efficient 16-point, 32-point and 64-point radix-22 FFT architectures reduce the total area by 32%, 19% and 11% respectively.

Design of Low Power Memory Architecture using 10t Sram Array

The main aim of electronics is to design low power devices due to the prevalent usage of powered gadget. Ultra low voltage operation of memory cells has become a subject of a lot of interest because of its applications in terribly low energy computing. The stable operation of static random access memory (SRAM) is important for the success of low voltage SRAM and it is achieved by parameter variations of scaled technologies. The power consumption and access time of the SRAM is also a complex parameter due to the unavoidable switching activities of the number of transistors used for different blocks like, SRAM cell, access transistors, pre-charge circuit, sense amplifier and decoders. It has been shown that conventional 6T SRAM fail to achieve low power and delay operation. The proposed 10T SRAM design gives an approach towards the hold power dissipation. The designed circuit has 10 transistors out of that 2 transistors are used as sleep transistor. The sleep transistors are used as switches. Such as header and footer switches and the switches are turned on during active mode of operations and turned off during idle or standby mode of operations. The designed SRAM cell also has conducting pMOS circuit, which can reduces the total power dissipation. The SRAM cell is simulated by using Cadence tool. A supply voltage of 1.8V is used which makes it enough for low power applications. The power obtained as 761.7mW, which reduces 15% of conventional 6T SRAM design. The delay obtained as 125.6ns, which reduces 45% of conventional 6T SRAM.

Design Of Dadda And Wallace Tree Multiplier Using Compressor Technique

The work portrays about the design of the Dadda multiplier using 4:2 compressor techniques. The three design techniques, namely conventional design, optimized design using exclusive OR with multiplexer and a further optimized design with less number of critical paths with gates are implemented. All the three designs are implemented in Dadda multiplier and wallace tree multiplier and their performances are compared. The performance metrics measured are area, power consumption, delay and transistor count and these parameters are efficient in dadda multiplier compared to wallace tree multiplier with the above three design techniques. The designs are using behavioral modeling and the results are taken in the 180nm Cadence tool. The result shows that the Dadda multiplier performs better in terms of delay, area and transistor count for all three designs than the Wallace tree multiplier.

An Innovative Low Power Reversible ALU for Quantum Processor using QCA

Landauer stated that “For irreversible computation each loss in information leads to loss of kTln2 joules of heat energy”. This has led to considerable interest in reversible logic. We know that ALU is the most basic part in any processor. Processor quality is determined based on its speed of operation. But, as the size of a processor decreases we face problems like power dissipation and greater delays. So, this paper presents an ALU implemented using reversible logic. This design is a simple way to reduce power dissipation and delay to a certain extent. Verilog HDL programming has been used to make this design. We have used XILINX and CADENCE tool to simulate this model and obtain power and delay analysis.

Optimization of CSA for Low Power and High-Speed using MTCMOS and GDI Techniques

The basic operation involved in any analog, digital, control system, DSP’s is addition. Performance and reliability of almost every digital system is depends on performance of adder. Over the decade, many adder architectures are proposed and still research work is going on adder to obtain the best results in power, delay and power delay product (PDP). In this paper we proposed one of the fastest adder architecture called Carry Select adder (CSA) and optimization is done for performance parameters like delay and power using GDI (Gate Diffused Input) and MTCMOS techniques. Implementation has been done in standard gpdk 90nm technology using Cadence tool.

Design and Performance Analysis of Hybrid Full Adder using Fin FET 40nm Technology

Designing a low power and energy efficient circuits in FinFET technology is of great Challenge. This paper presents the internal logic structure and circuit operation using the devices, CMOS and FinFETs for designing the hybrid adder cells. At transistor level, CMOS and FinFET based hybrid full adder (HFA) and improved hybrid full adder (IHFA) is designed. Simulations are carried out using the cadence tool in UMC 40nm and the performance analysis of these HFA and IHFA are compared with the 40nm FinFET technology. It is observed that IHFA is better when compared with the HFA in terms of propagation delay, power consumption and energy delay product. IHFA achieves the higher drive current and low leakage power for better mobility and transistor scaling as compared with HFA.

Design And Analysis Of RHBD Memory Cells And 4x4 RHBD 10T Memory Cell Architecture

CMOS technology plays an important role in the modern electronics world. CMOS technology also plays significant role in aerospace applications. To store data, memories are widely used as the medium in aerospace applications. SRAM cells are the memories made by the CMOS technology. The most vital issues faced by memories are due to single event upsets (SEUs) which are induced by radiation particles. The SEU’s due to increase in densities and SEU’s. There is a decrease in critical charge and supply voltage in CMOS process technology. There is a need for a technique which can to tolerate these SEU’s in such aerospace applications. Which are in the environment of complex celestial radiation? The technique which is considered for such environment is radiation-hardened by design (RHBD) with soft error robustness. This paper aims at is proposing an area efficient and high reliable RHBD memory cell for the above said application using 45nm technology in Cadence Tool. Depending on power, write/read time, the layout area of 14T, 12T and 10T RHBD memory cells and their performance on power for read/write operations are observed. A comparative study is also done on these memory cells based the parameters considered.

Design of Fast Efficient Radix-16 Sequential Multiplier

Multiplication is an important function in computer arithmetic operations. The multiplication process will be done by the shift-and-add sequential multiplication procedure. Radix-16 sequential multiplier design generates the radix-16 partial products as two low (L) and high (H) components. In order to reduce cycle time, Brent-Kung adder and two radix 16 carry-save adders are used to generate radix-16 partial products. The proposed design of radix-16 sequential multiplier is efficient over previous designs and comparison depicts ADP and PDP of existing method are 11.22% and 8.45% than proposed method. However, the Excess area-Delay product and Excess-power-Delay product is also lowered. The design is carried out in Xilinx ISE 14.5 software and cadence tool for simulation and synthesis results. Fast efficient radix-16 sequential multiplier can be used in many digital signal processing applications.

Beamforming, null-steering, and simultaneous spatial and frequency domain filtering in integrated phased array systems

In the case that phased array systems are not capable of attenuating interferences, Radio Frequency (RF) front-ends and Analog Digital Converters (ADCs) with a large dynamic range are required to avoid saturation of the receiver. This leads to a higher power consumption. In this paper, employing N-path circuits in Mixer-First receivers, a novel method is introduced in which spatial and frequency blockers are eliminated right before entering the system on the antennas input. In fact using this technique, adjustable spatial notch filter and band-pass frequency filter are implemented to suppress spatial and frequency interferences. The proposed method enhances the robustness and effectiveness of phased array systems in the presence of blockers. The proposed technique is flexible, tunable across operating frequency from 0.2 to 3 GHz, low cost, with 0.66 × 0.58 mm2 layout area, and 72 mW power consumption with a supply voltage of 1.8 V. The achieved out-of-band input third-order intercept point of the proposed circuit is +25 dBm, and the NF of the system is approximately 4 dB. Using passive mixers provide high linearity of up to IIP3 = +2 dBm in-band. These advantages are verified through system and circuit simulations using Matlab and Cadence tools implemented in 0.18 μm CMOS technology.